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c7111c1318
The problem we can't take advantage of lowest priority delivery mode if the vectors are allocated for only one cpu at a time. Nor can we work around hardware that assumes lowest priority delivery mode is always used with several cpus. So this patch introduces the concept of a vector_allocation_domain. A set of cpus that will receive an irq on the same vector. Currently the code for implementing this is placed in the genapic structure so we can vary this depending on how we are using the io_apics. This allows us to restore the previous behaviour of genapic_flat without removing the benefits of having separate vector allocation for large machines. This should also fix the problem report where a hyperthreaded cpu was receving the irq on the wrong hyperthread when in logical delivery mode because the previous behaviour is restored. This patch properly records our allocation of the first 16 irqs to the first 16 available vectors on all cpus. This should be fine but it may run into problems with multiple interrupts at the same interrupt level. Except for some badly maintained comments in the code and the behaviour of the interrupt allocator I have no real understanding of that problem. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Acked-by: Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
137 lines
3.6 KiB
C
137 lines
3.6 KiB
C
/*
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* Copyright 2004 James Cleverdon, IBM.
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* Subject to the GNU Public License, v.2
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*
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* Clustered APIC subarch code. Up to 255 CPUs, physical delivery.
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* (A more realistic maximum is around 230 CPUs.)
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*
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* Hacked for x86-64 by James Cleverdon from i386 architecture code by
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* Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
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* James Cleverdon.
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*/
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#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <asm/smp.h>
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#include <asm/ipi.h>
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/*
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* Set up the logical destination ID.
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*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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static void cluster_init_apic_ldr(void)
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{
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unsigned long val, id;
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long i, count;
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u8 lid;
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u8 my_id = hard_smp_processor_id();
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u8 my_cluster = APIC_CLUSTER(my_id);
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/* Create logical APIC IDs by counting CPUs already in cluster. */
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for (count = 0, i = NR_CPUS; --i >= 0; ) {
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lid = x86_cpu_to_log_apicid[i];
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if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster)
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++count;
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}
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/*
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* We only have a 4 wide bitmap in cluster mode. There's no way
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* to get above 60 CPUs and still give each one it's own bit.
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* But, we're using physical IRQ delivery, so we don't care.
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* Use bit 3 for the 4th through Nth CPU in each cluster.
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*/
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if (count >= XAPIC_DEST_CPUS_SHIFT)
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count = 3;
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id = my_cluster | (1UL << count);
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x86_cpu_to_log_apicid[smp_processor_id()] = id;
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apic_write(APIC_DFR, APIC_DFR_CLUSTER);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(id);
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apic_write(APIC_LDR, val);
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}
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/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
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static cpumask_t cluster_target_cpus(void)
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{
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return cpumask_of_cpu(0);
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}
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static cpumask_t cluster_vector_allocation_domain(int cpu)
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{
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cpumask_t domain = CPU_MASK_NONE;
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cpu_set(cpu, domain);
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return domain;
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}
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static void cluster_send_IPI_mask(cpumask_t mask, int vector)
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{
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send_IPI_mask_sequence(mask, vector);
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}
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static void cluster_send_IPI_allbutself(int vector)
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{
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cpumask_t mask = cpu_online_map;
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cpu_clear(smp_processor_id(), mask);
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if (!cpus_empty(mask))
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cluster_send_IPI_mask(mask, vector);
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}
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static void cluster_send_IPI_all(int vector)
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{
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cluster_send_IPI_mask(cpu_online_map, vector);
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}
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static int cluster_apic_id_registered(void)
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{
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return 1;
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}
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static unsigned int cluster_cpu_mask_to_apicid(cpumask_t cpumask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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cpu = first_cpu(cpumask);
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if ((unsigned)cpu < NR_CPUS)
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return x86_cpu_to_apicid[cpu];
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else
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return BAD_APICID;
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}
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/* cpuid returns the value latched in the HW at reset, not the APIC ID
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* register's value. For any box whose BIOS changes APIC IDs, like
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* clustered APIC systems, we must use hard_smp_processor_id.
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*
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* See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
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*/
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static unsigned int phys_pkg_id(int index_msb)
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{
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return hard_smp_processor_id() >> index_msb;
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}
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struct genapic apic_cluster = {
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.name = "clustered",
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.int_delivery_mode = dest_Fixed,
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.int_dest_mode = (APIC_DEST_PHYSICAL != 0),
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.target_cpus = cluster_target_cpus,
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.vector_allocation_domain = cluster_vector_allocation_domain,
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.apic_id_registered = cluster_apic_id_registered,
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.init_apic_ldr = cluster_init_apic_ldr,
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.send_IPI_all = cluster_send_IPI_all,
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.send_IPI_allbutself = cluster_send_IPI_allbutself,
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.send_IPI_mask = cluster_send_IPI_mask,
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.cpu_mask_to_apicid = cluster_cpu_mask_to_apicid,
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.phys_pkg_id = phys_pkg_id,
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};
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