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![Robert Richter](/assets/img/avatar_default.png)
boot_cpu_id is there for historical reasons and was renamed to
boot_cpu_physical_apicid in patch:
c70dcb7
x86: change boot_cpu_id to boot_cpu_physical_apicid
However, there are some remaining occurrences of boot_cpu_id that are
never touched in the kernel and thus its value is always 0.
This patch removes boot_cpu_id completely.
Signed-off-by: Robert Richter <robert.richter@amd.com>
LKML-Reference: <1279731838-1522-8-git-send-email-robert.richter@amd.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
764 lines
21 KiB
C
764 lines
21 KiB
C
/*
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* apb_timer.c: Driver for Langwell APB timers
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*
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* (C) Copyright 2009 Intel Corporation
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* Author: Jacob Pan (jacob.jun.pan@intel.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*
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* Note:
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* Langwell is the south complex of Intel Moorestown MID platform. There are
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* eight external timers in total that can be used by the operating system.
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* The timer information, such as frequency and addresses, is provided to the
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* OS via SFI tables.
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* Timer interrupts are routed via FW/HW emulated IOAPIC independently via
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* individual redirection table entries (RTE).
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* Unlike HPET, there is no master counter, therefore one of the timers are
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* used as clocksource. The overall allocation looks like:
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* - timer 0 - NR_CPUs for per cpu timer
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* - one timer for clocksource
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* - one timer for watchdog driver.
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* It is also worth notice that APB timer does not support true one-shot mode,
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* free-running mode will be used here to emulate one-shot mode.
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* APB timer can also be used as broadcast timer along with per cpu local APIC
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* timer, but by default APB timer has higher rating than local APIC timers.
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*/
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/sysdev.h>
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#include <linux/slab.h>
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#include <linux/pm.h>
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#include <linux/pci.h>
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#include <linux/sfi.h>
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#include <linux/interrupt.h>
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#include <linux/cpu.h>
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#include <linux/irq.h>
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#include <asm/fixmap.h>
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#include <asm/apb_timer.h>
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#include <asm/mrst.h>
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#define APBT_MASK CLOCKSOURCE_MASK(32)
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#define APBT_SHIFT 22
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#define APBT_CLOCKEVENT_RATING 110
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#define APBT_CLOCKSOURCE_RATING 250
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#define APBT_MIN_DELTA_USEC 200
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#define EVT_TO_APBT_DEV(evt) container_of(evt, struct apbt_dev, evt)
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#define APBT_CLOCKEVENT0_NUM (0)
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#define APBT_CLOCKEVENT1_NUM (1)
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#define APBT_CLOCKSOURCE_NUM (2)
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static unsigned long apbt_address;
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static int apb_timer_block_enabled;
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static void __iomem *apbt_virt_address;
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static int phy_cs_timer_id;
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/*
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* Common DW APB timer info
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*/
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static uint64_t apbt_freq;
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static void apbt_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt);
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static int apbt_next_event(unsigned long delta,
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struct clock_event_device *evt);
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static cycle_t apbt_read_clocksource(struct clocksource *cs);
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static void apbt_restart_clocksource(struct clocksource *cs);
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struct apbt_dev {
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struct clock_event_device evt;
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unsigned int num;
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int cpu;
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unsigned int irq;
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unsigned int tick;
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unsigned int count;
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unsigned int flags;
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char name[10];
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};
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static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
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#ifdef CONFIG_SMP
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static unsigned int apbt_num_timers_used;
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static struct apbt_dev *apbt_devs;
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#endif
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static inline unsigned long apbt_readl_reg(unsigned long a)
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{
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return readl(apbt_virt_address + a);
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}
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static inline void apbt_writel_reg(unsigned long d, unsigned long a)
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{
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writel(d, apbt_virt_address + a);
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}
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static inline unsigned long apbt_readl(int n, unsigned long a)
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{
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return readl(apbt_virt_address + a + n * APBTMRS_REG_SIZE);
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}
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static inline void apbt_writel(int n, unsigned long d, unsigned long a)
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{
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writel(d, apbt_virt_address + a + n * APBTMRS_REG_SIZE);
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}
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static inline void apbt_set_mapping(void)
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{
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struct sfi_timer_table_entry *mtmr;
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if (apbt_virt_address) {
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pr_debug("APBT base already mapped\n");
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return;
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}
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mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
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if (mtmr == NULL) {
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printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
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APBT_CLOCKEVENT0_NUM);
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return;
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}
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apbt_address = (unsigned long)mtmr->phys_addr;
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if (!apbt_address) {
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printk(KERN_WARNING "No timer base from SFI, use default\n");
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apbt_address = APBT_DEFAULT_BASE;
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}
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apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE);
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if (apbt_virt_address) {
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pr_debug("Mapped APBT physical addr %p at virtual addr %p\n",\
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(void *)apbt_address, (void *)apbt_virt_address);
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} else {
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pr_debug("Failed mapping APBT phy address at %p\n",\
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(void *)apbt_address);
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goto panic_noapbt;
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}
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apbt_freq = mtmr->freq_hz / USEC_PER_SEC;
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sfi_free_mtmr(mtmr);
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/* Now figure out the physical timer id for clocksource device */
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mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM);
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if (mtmr == NULL)
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goto panic_noapbt;
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/* Now figure out the physical timer id */
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phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff)
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/ APBTMRS_REG_SIZE;
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pr_debug("Use timer %d for clocksource\n", phy_cs_timer_id);
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return;
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panic_noapbt:
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panic("Failed to setup APB system timer\n");
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}
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static inline void apbt_clear_mapping(void)
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{
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iounmap(apbt_virt_address);
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apbt_virt_address = NULL;
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}
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/*
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* APBT timer interrupt enable / disable
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*/
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static inline int is_apbt_capable(void)
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{
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return apbt_virt_address ? 1 : 0;
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}
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static struct clocksource clocksource_apbt = {
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.name = "apbt",
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.rating = APBT_CLOCKSOURCE_RATING,
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.read = apbt_read_clocksource,
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.mask = APBT_MASK,
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.shift = APBT_SHIFT,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.resume = apbt_restart_clocksource,
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};
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/* boot APB clock event device */
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static struct clock_event_device apbt_clockevent = {
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.name = "apbt0",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = apbt_set_mode,
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.set_next_event = apbt_next_event,
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.shift = APBT_SHIFT,
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.irq = 0,
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.rating = APBT_CLOCKEVENT_RATING,
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};
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/*
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* start count down from 0xffff_ffff. this is done by toggling the enable bit
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* then load initial load count to ~0.
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*/
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static void apbt_start_counter(int n)
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{
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unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
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ctrl &= ~APBTMR_CONTROL_ENABLE;
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apbt_writel(n, ctrl, APBTMR_N_CONTROL);
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apbt_writel(n, ~0, APBTMR_N_LOAD_COUNT);
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/* enable, mask interrupt */
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ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
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ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
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apbt_writel(n, ctrl, APBTMR_N_CONTROL);
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/* read it once to get cached counter value initialized */
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apbt_read_clocksource(&clocksource_apbt);
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}
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static irqreturn_t apbt_interrupt_handler(int irq, void *data)
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{
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struct apbt_dev *dev = (struct apbt_dev *)data;
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struct clock_event_device *aevt = &dev->evt;
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if (!aevt->event_handler) {
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printk(KERN_INFO "Spurious APBT timer interrupt on %d\n",
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dev->num);
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return IRQ_NONE;
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}
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aevt->event_handler(aevt);
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return IRQ_HANDLED;
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}
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static void apbt_restart_clocksource(struct clocksource *cs)
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{
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apbt_start_counter(phy_cs_timer_id);
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}
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/* Setup IRQ routing via IOAPIC */
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#ifdef CONFIG_SMP
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static void apbt_setup_irq(struct apbt_dev *adev)
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{
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struct irq_chip *chip;
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struct irq_desc *desc;
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/* timer0 irq has been setup early */
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if (adev->irq == 0)
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return;
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desc = irq_to_desc(adev->irq);
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chip = get_irq_chip(adev->irq);
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disable_irq(adev->irq);
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desc->status |= IRQ_MOVE_PCNTXT;
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irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
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/* APB timer irqs are set up as mp_irqs, timer is edge triggerred */
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set_irq_chip_and_handler_name(adev->irq, chip, handle_edge_irq, "edge");
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enable_irq(adev->irq);
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if (system_state == SYSTEM_BOOTING)
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if (request_irq(adev->irq, apbt_interrupt_handler,
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IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
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adev->name, adev)) {
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printk(KERN_ERR "Failed request IRQ for APBT%d\n",
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adev->num);
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}
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}
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#endif
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static void apbt_enable_int(int n)
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{
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unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
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/* clear pending intr */
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apbt_readl(n, APBTMR_N_EOI);
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ctrl &= ~APBTMR_CONTROL_INT;
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apbt_writel(n, ctrl, APBTMR_N_CONTROL);
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}
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static void apbt_disable_int(int n)
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{
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unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
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ctrl |= APBTMR_CONTROL_INT;
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apbt_writel(n, ctrl, APBTMR_N_CONTROL);
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}
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static int __init apbt_clockevent_register(void)
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{
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struct sfi_timer_table_entry *mtmr;
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struct apbt_dev *adev = &__get_cpu_var(cpu_apbt_dev);
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mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
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if (mtmr == NULL) {
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printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
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APBT_CLOCKEVENT0_NUM);
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return -ENODEV;
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}
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/*
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* We need to calculate the scaled math multiplication factor for
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* nanosecond to apbt tick conversion.
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* mult = (nsec/cycle)*2^APBT_SHIFT
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*/
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apbt_clockevent.mult = div_sc((unsigned long) mtmr->freq_hz
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, NSEC_PER_SEC, APBT_SHIFT);
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/* Calculate the min / max delta */
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apbt_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
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&apbt_clockevent);
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apbt_clockevent.min_delta_ns = clockevent_delta2ns(
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APBT_MIN_DELTA_USEC*apbt_freq,
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&apbt_clockevent);
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/*
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* Start apbt with the boot cpu mask and make it
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* global if not used for per cpu timer.
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*/
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apbt_clockevent.cpumask = cpumask_of(smp_processor_id());
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adev->num = smp_processor_id();
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memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
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if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
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apbt_clockevent.rating = APBT_CLOCKEVENT_RATING - 100;
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global_clock_event = &adev->evt;
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printk(KERN_DEBUG "%s clockevent registered as global\n",
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global_clock_event->name);
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}
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if (request_irq(apbt_clockevent.irq, apbt_interrupt_handler,
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IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
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apbt_clockevent.name, adev)) {
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printk(KERN_ERR "Failed request IRQ for APBT%d\n",
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apbt_clockevent.irq);
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}
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clockevents_register_device(&adev->evt);
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/* Start APBT 0 interrupts */
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apbt_enable_int(APBT_CLOCKEVENT0_NUM);
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sfi_free_mtmr(mtmr);
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return 0;
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}
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#ifdef CONFIG_SMP
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/* Should be called with per cpu */
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void apbt_setup_secondary_clock(void)
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{
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struct apbt_dev *adev;
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struct clock_event_device *aevt;
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int cpu;
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/* Don't register boot CPU clockevent */
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cpu = smp_processor_id();
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if (!cpu)
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return;
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/*
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* We need to calculate the scaled math multiplication factor for
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* nanosecond to apbt tick conversion.
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* mult = (nsec/cycle)*2^APBT_SHIFT
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*/
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printk(KERN_INFO "Init per CPU clockevent %d\n", cpu);
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adev = &per_cpu(cpu_apbt_dev, cpu);
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aevt = &adev->evt;
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memcpy(aevt, &apbt_clockevent, sizeof(*aevt));
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aevt->cpumask = cpumask_of(cpu);
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aevt->name = adev->name;
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aevt->mode = CLOCK_EVT_MODE_UNUSED;
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printk(KERN_INFO "Registering CPU %d clockevent device %s, mask %08x\n",
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cpu, aevt->name, *(u32 *)aevt->cpumask);
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apbt_setup_irq(adev);
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clockevents_register_device(aevt);
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apbt_enable_int(cpu);
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return;
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}
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/*
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* this notify handler process CPU hotplug events. in case of S0i3, nonboot
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* cpus are disabled/enabled frequently, for performance reasons, we keep the
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* per cpu timer irq registered so that we do need to do free_irq/request_irq.
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*
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* TODO: it might be more reliable to directly disable percpu clockevent device
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* without the notifier chain. currently, cpu 0 may get interrupts from other
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* cpu timers during the offline process due to the ordering of notification.
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* the extra interrupt is harmless.
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*/
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static int apbt_cpuhp_notify(struct notifier_block *n,
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unsigned long action, void *hcpu)
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{
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unsigned long cpu = (unsigned long)hcpu;
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struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu);
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switch (action & 0xf) {
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case CPU_DEAD:
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apbt_disable_int(cpu);
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if (system_state == SYSTEM_RUNNING)
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pr_debug("skipping APBT CPU %lu offline\n", cpu);
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else if (adev) {
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pr_debug("APBT clockevent for cpu %lu offline\n", cpu);
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free_irq(adev->irq, adev);
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}
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break;
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default:
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pr_debug(KERN_INFO "APBT notified %lu, no action\n", action);
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}
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return NOTIFY_OK;
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}
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|
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static __init int apbt_late_init(void)
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{
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if (mrst_timer_options == MRST_TIMER_LAPIC_APBT ||
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!apb_timer_block_enabled)
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return 0;
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/* This notifier should be called after workqueue is ready */
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hotcpu_notifier(apbt_cpuhp_notify, -20);
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return 0;
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}
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fs_initcall(apbt_late_init);
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#else
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|
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void apbt_setup_secondary_clock(void) {}
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|
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#endif /* CONFIG_SMP */
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|
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static void apbt_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
|
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{
|
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unsigned long ctrl;
|
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uint64_t delta;
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int timer_num;
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struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
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|
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BUG_ON(!apbt_virt_address);
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|
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timer_num = adev->num;
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pr_debug("%s CPU %d timer %d mode=%d\n",
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__func__, first_cpu(*evt->cpumask), timer_num, mode);
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|
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * apbt_clockevent.mult;
|
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delta >>= apbt_clockevent.shift;
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ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
|
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ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
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apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
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/*
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* DW APB p. 46, have to disable timer before load counter,
|
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* may cause sync problem.
|
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*/
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ctrl &= ~APBTMR_CONTROL_ENABLE;
|
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apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
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udelay(1);
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pr_debug("Setting clock period %d for HZ %d\n", (int)delta, HZ);
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apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT);
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ctrl |= APBTMR_CONTROL_ENABLE;
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apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
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break;
|
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/* APB timer does not have one-shot mode, use free running mode */
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case CLOCK_EVT_MODE_ONESHOT:
|
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ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
|
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/*
|
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* set free running mode, this mode will let timer reload max
|
|
* timeout which will give time (3min on 25MHz clock) to rearm
|
|
* the next event, therefore emulate the one-shot mode.
|
|
*/
|
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ctrl &= ~APBTMR_CONTROL_ENABLE;
|
|
ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
|
|
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
/* write again to set free running mode */
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
|
|
/*
|
|
* DW APB p. 46, load counter with all 1s before starting free
|
|
* running mode.
|
|
*/
|
|
apbt_writel(timer_num, ~0, APBTMR_N_LOAD_COUNT);
|
|
ctrl &= ~APBTMR_CONTROL_INT;
|
|
ctrl |= APBTMR_CONTROL_ENABLE;
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
break;
|
|
|
|
case CLOCK_EVT_MODE_UNUSED:
|
|
case CLOCK_EVT_MODE_SHUTDOWN:
|
|
apbt_disable_int(timer_num);
|
|
ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
|
|
ctrl &= ~APBTMR_CONTROL_ENABLE;
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
break;
|
|
|
|
case CLOCK_EVT_MODE_RESUME:
|
|
apbt_enable_int(timer_num);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int apbt_next_event(unsigned long delta,
|
|
struct clock_event_device *evt)
|
|
{
|
|
unsigned long ctrl;
|
|
int timer_num;
|
|
|
|
struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
|
|
|
|
timer_num = adev->num;
|
|
/* Disable timer */
|
|
ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
|
|
ctrl &= ~APBTMR_CONTROL_ENABLE;
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
/* write new count */
|
|
apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT);
|
|
ctrl |= APBTMR_CONTROL_ENABLE;
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* APB timer clock is not in sync with pclk on Langwell, which translates to
|
|
* unreliable read value caused by sampling error. the error does not add up
|
|
* overtime and only happens when sampling a 0 as a 1 by mistake. so the time
|
|
* would go backwards. the following code is trying to prevent time traveling
|
|
* backwards. little bit paranoid.
|
|
*/
|
|
static cycle_t apbt_read_clocksource(struct clocksource *cs)
|
|
{
|
|
unsigned long t0, t1, t2;
|
|
static unsigned long last_read;
|
|
|
|
bad_count:
|
|
t1 = apbt_readl(phy_cs_timer_id,
|
|
APBTMR_N_CURRENT_VALUE);
|
|
t2 = apbt_readl(phy_cs_timer_id,
|
|
APBTMR_N_CURRENT_VALUE);
|
|
if (unlikely(t1 < t2)) {
|
|
pr_debug("APBT: read current count error %lx:%lx:%lx\n",
|
|
t1, t2, t2 - t1);
|
|
goto bad_count;
|
|
}
|
|
/*
|
|
* check against cached last read, makes sure time does not go back.
|
|
* it could be a normal rollover but we will do tripple check anyway
|
|
*/
|
|
if (unlikely(t2 > last_read)) {
|
|
/* check if we have a normal rollover */
|
|
unsigned long raw_intr_status =
|
|
apbt_readl_reg(APBTMRS_RAW_INT_STATUS);
|
|
/*
|
|
* cs timer interrupt is masked but raw intr bit is set if
|
|
* rollover occurs. then we read EOI reg to clear it.
|
|
*/
|
|
if (raw_intr_status & (1 << phy_cs_timer_id)) {
|
|
apbt_readl(phy_cs_timer_id, APBTMR_N_EOI);
|
|
goto out;
|
|
}
|
|
pr_debug("APB CS going back %lx:%lx:%lx ",
|
|
t2, last_read, t2 - last_read);
|
|
bad_count_x3:
|
|
pr_debug(KERN_INFO "tripple check enforced\n");
|
|
t0 = apbt_readl(phy_cs_timer_id,
|
|
APBTMR_N_CURRENT_VALUE);
|
|
udelay(1);
|
|
t1 = apbt_readl(phy_cs_timer_id,
|
|
APBTMR_N_CURRENT_VALUE);
|
|
udelay(1);
|
|
t2 = apbt_readl(phy_cs_timer_id,
|
|
APBTMR_N_CURRENT_VALUE);
|
|
if ((t2 > t1) || (t1 > t0)) {
|
|
printk(KERN_ERR "Error: APB CS tripple check failed\n");
|
|
goto bad_count_x3;
|
|
}
|
|
}
|
|
out:
|
|
last_read = t2;
|
|
return (cycle_t)~t2;
|
|
}
|
|
|
|
static int apbt_clocksource_register(void)
|
|
{
|
|
u64 start, now;
|
|
cycle_t t1;
|
|
|
|
/* Start the counter, use timer 2 as source, timer 0/1 for event */
|
|
apbt_start_counter(phy_cs_timer_id);
|
|
|
|
/* Verify whether apbt counter works */
|
|
t1 = apbt_read_clocksource(&clocksource_apbt);
|
|
rdtscll(start);
|
|
|
|
/*
|
|
* We don't know the TSC frequency yet, but waiting for
|
|
* 200000 TSC cycles is safe:
|
|
* 4 GHz == 50us
|
|
* 1 GHz == 200us
|
|
*/
|
|
do {
|
|
rep_nop();
|
|
rdtscll(now);
|
|
} while ((now - start) < 200000UL);
|
|
|
|
/* APBT is the only always on clocksource, it has to work! */
|
|
if (t1 == apbt_read_clocksource(&clocksource_apbt))
|
|
panic("APBT counter not counting. APBT disabled\n");
|
|
|
|
/*
|
|
* initialize and register APBT clocksource
|
|
* convert that to ns/clock cycle
|
|
* mult = (ns/c) * 2^APBT_SHIFT
|
|
*/
|
|
clocksource_apbt.mult = div_sc(MSEC_PER_SEC,
|
|
(unsigned long) apbt_freq, APBT_SHIFT);
|
|
clocksource_register(&clocksource_apbt);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Early setup the APBT timer, only use timer 0 for booting then switch to
|
|
* per CPU timer if possible.
|
|
* returns 1 if per cpu apbt is setup
|
|
* returns 0 if no per cpu apbt is chosen
|
|
* panic if set up failed, this is the only platform timer on Moorestown.
|
|
*/
|
|
void __init apbt_time_init(void)
|
|
{
|
|
#ifdef CONFIG_SMP
|
|
int i;
|
|
struct sfi_timer_table_entry *p_mtmr;
|
|
unsigned int percpu_timer;
|
|
struct apbt_dev *adev;
|
|
#endif
|
|
|
|
if (apb_timer_block_enabled)
|
|
return;
|
|
apbt_set_mapping();
|
|
if (apbt_virt_address) {
|
|
pr_debug("Found APBT version 0x%lx\n",\
|
|
apbt_readl_reg(APBTMRS_COMP_VERSION));
|
|
} else
|
|
goto out_noapbt;
|
|
/*
|
|
* Read the frequency and check for a sane value, for ESL model
|
|
* we extend the possible clock range to allow time scaling.
|
|
*/
|
|
|
|
if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
|
|
pr_debug("APBT has invalid freq 0x%llx\n", apbt_freq);
|
|
goto out_noapbt;
|
|
}
|
|
if (apbt_clocksource_register()) {
|
|
pr_debug("APBT has failed to register clocksource\n");
|
|
goto out_noapbt;
|
|
}
|
|
if (!apbt_clockevent_register())
|
|
apb_timer_block_enabled = 1;
|
|
else {
|
|
pr_debug("APBT has failed to register clockevent\n");
|
|
goto out_noapbt;
|
|
}
|
|
#ifdef CONFIG_SMP
|
|
/* kernel cmdline disable apb timer, so we will use lapic timers */
|
|
if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
|
|
printk(KERN_INFO "apbt: disabled per cpu timer\n");
|
|
return;
|
|
}
|
|
pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus());
|
|
if (num_possible_cpus() <= sfi_mtimer_num) {
|
|
percpu_timer = 1;
|
|
apbt_num_timers_used = num_possible_cpus();
|
|
} else {
|
|
percpu_timer = 0;
|
|
apbt_num_timers_used = 1;
|
|
adev = &per_cpu(cpu_apbt_dev, 0);
|
|
adev->flags &= ~APBT_DEV_USED;
|
|
}
|
|
pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
|
|
|
|
/* here we set up per CPU timer data structure */
|
|
apbt_devs = kzalloc(sizeof(struct apbt_dev) * apbt_num_timers_used,
|
|
GFP_KERNEL);
|
|
if (!apbt_devs) {
|
|
printk(KERN_ERR "Failed to allocate APB timer devices\n");
|
|
return;
|
|
}
|
|
for (i = 0; i < apbt_num_timers_used; i++) {
|
|
adev = &per_cpu(cpu_apbt_dev, i);
|
|
adev->num = i;
|
|
adev->cpu = i;
|
|
p_mtmr = sfi_get_mtmr(i);
|
|
if (p_mtmr) {
|
|
adev->tick = p_mtmr->freq_hz;
|
|
adev->irq = p_mtmr->irq;
|
|
} else
|
|
printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
|
|
adev->count = 0;
|
|
sprintf(adev->name, "apbt%d", i);
|
|
}
|
|
#endif
|
|
|
|
return;
|
|
|
|
out_noapbt:
|
|
apbt_clear_mapping();
|
|
apb_timer_block_enabled = 0;
|
|
panic("failed to enable APB timer\n");
|
|
}
|
|
|
|
static inline void apbt_disable(int n)
|
|
{
|
|
if (is_apbt_capable()) {
|
|
unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
|
|
ctrl &= ~APBTMR_CONTROL_ENABLE;
|
|
apbt_writel(n, ctrl, APBTMR_N_CONTROL);
|
|
}
|
|
}
|
|
|
|
/* called before apb_timer_enable, use early map */
|
|
unsigned long apbt_quick_calibrate()
|
|
{
|
|
int i, scale;
|
|
u64 old, new;
|
|
cycle_t t1, t2;
|
|
unsigned long khz = 0;
|
|
u32 loop, shift;
|
|
|
|
apbt_set_mapping();
|
|
apbt_start_counter(phy_cs_timer_id);
|
|
|
|
/* check if the timer can count down, otherwise return */
|
|
old = apbt_read_clocksource(&clocksource_apbt);
|
|
i = 10000;
|
|
while (--i) {
|
|
if (old != apbt_read_clocksource(&clocksource_apbt))
|
|
break;
|
|
}
|
|
if (!i)
|
|
goto failed;
|
|
|
|
/* count 16 ms */
|
|
loop = (apbt_freq * 1000) << 4;
|
|
|
|
/* restart the timer to ensure it won't get to 0 in the calibration */
|
|
apbt_start_counter(phy_cs_timer_id);
|
|
|
|
old = apbt_read_clocksource(&clocksource_apbt);
|
|
old += loop;
|
|
|
|
t1 = __native_read_tsc();
|
|
|
|
do {
|
|
new = apbt_read_clocksource(&clocksource_apbt);
|
|
} while (new < old);
|
|
|
|
t2 = __native_read_tsc();
|
|
|
|
shift = 5;
|
|
if (unlikely(loop >> shift == 0)) {
|
|
printk(KERN_INFO
|
|
"APBT TSC calibration failed, not enough resolution\n");
|
|
return 0;
|
|
}
|
|
scale = (int)div_u64((t2 - t1), loop >> shift);
|
|
khz = (scale * apbt_freq * 1000) >> shift;
|
|
printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz);
|
|
return khz;
|
|
failed:
|
|
return 0;
|
|
}
|