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![Ville Syrjälä](/assets/img/avatar_default.png)
Hoist the intel_de.h include from intel_display_types.h one level up. I need this in order to untangle the include order so that I can add tracepoints into intel_de.h. This little cocci script did most of the work for me: @find@ @@ ( intel_de_read(...) | intel_de_read_fw(...) | intel_de_write(...) | intel_de_write_fw(...) ) @has_include@ @@ ( #include "intel_de.h" | #include "display/intel_de.h" ) @depends on find && !has_include@ @@ + #include "intel_de.h" #include "intel_display_types.h" @depends on find && !has_include@ @@ + #include "display/intel_de.h" #include "display/intel_display_types.h" Cc: Cooper Chiou <cooper.chiou@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210430143945.6776-1-ville.syrjala@linux.intel.com
1433 lines
41 KiB
C
1433 lines
41 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*
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* DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).
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*/
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#include "g4x_dp.h"
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#include "intel_audio.h"
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#include "intel_connector.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_dp.h"
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#include "intel_dp_link_training.h"
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#include "intel_dpio_phy.h"
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#include "intel_fifo_underrun.h"
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#include "intel_hdmi.h"
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#include "intel_hotplug.h"
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#include "intel_panel.h"
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#include "intel_pps.h"
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#include "intel_sideband.h"
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struct dp_link_dpll {
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int clock;
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struct dpll dpll;
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};
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static const struct dp_link_dpll g4x_dpll[] = {
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{ 162000,
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{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
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{ 270000,
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{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
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};
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static const struct dp_link_dpll pch_dpll[] = {
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{ 162000,
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{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
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{ 270000,
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{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
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};
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static const struct dp_link_dpll vlv_dpll[] = {
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{ 162000,
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{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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{ 270000,
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{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
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};
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/*
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* CHV supports eDP 1.4 that have more link rates.
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* Below only provides the fixed rate but exclude variable rate.
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*/
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static const struct dp_link_dpll chv_dpll[] = {
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/*
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* CHV requires to program fractional division for m2.
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* m2 is stored in fixed point format using formula below
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* (m2_int << 22) | m2_fraction
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*/
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{ 162000, /* m2_int = 32, m2_fraction = 1677722 */
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{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
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{ 270000, /* m2_int = 27, m2_fraction = 0 */
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{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
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};
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const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)
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{
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return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;
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}
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void g4x_dp_set_clock(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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const struct dp_link_dpll *divisor = NULL;
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int i, count = 0;
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if (IS_G4X(dev_priv)) {
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divisor = g4x_dpll;
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count = ARRAY_SIZE(g4x_dpll);
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} else if (HAS_PCH_SPLIT(dev_priv)) {
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divisor = pch_dpll;
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count = ARRAY_SIZE(pch_dpll);
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} else if (IS_CHERRYVIEW(dev_priv)) {
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divisor = chv_dpll;
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count = ARRAY_SIZE(chv_dpll);
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} else if (IS_VALLEYVIEW(dev_priv)) {
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divisor = vlv_dpll;
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count = ARRAY_SIZE(vlv_dpll);
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}
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if (divisor && count) {
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for (i = 0; i < count; i++) {
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if (pipe_config->port_clock == divisor[i].clock) {
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pipe_config->dpll = divisor[i].dpll;
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pipe_config->clock_set = true;
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break;
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}
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}
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}
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}
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static void intel_dp_prepare(struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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enum port port = encoder->port;
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
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const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
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intel_dp_set_link_params(intel_dp,
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pipe_config->port_clock,
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pipe_config->lane_count);
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/*
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* There are four kinds of DP registers:
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* IBX PCH
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* SNB CPU
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* IVB CPU
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* CPT PCH
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*
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* IBX PCH and CPU are the same for almost everything,
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* except that the CPU DP PLL is configured in this
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* register
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*
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* CPT PCH is quite different, having many bits moved
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* to the TRANS_DP_CTL register instead. That
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* configuration happens (oddly) in ilk_pch_enable
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*/
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/* Preserve the BIOS-computed detected bit. This is
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* supposed to be read-only.
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*/
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intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
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/* Handle DP bits in common between all three register formats */
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intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
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intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
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/* Split out the IBX/CPU vs CPT settings */
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if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
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if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
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intel_dp->DP |= DP_SYNC_HS_HIGH;
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if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
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intel_dp->DP |= DP_SYNC_VS_HIGH;
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intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
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if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
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intel_dp->DP |= DP_ENHANCED_FRAMING;
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intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
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} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
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u32 trans_dp;
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intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
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trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
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if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
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trans_dp |= TRANS_DP_ENH_FRAMING;
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else
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trans_dp &= ~TRANS_DP_ENH_FRAMING;
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intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
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} else {
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if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
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intel_dp->DP |= DP_COLOR_RANGE_16_235;
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if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
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intel_dp->DP |= DP_SYNC_HS_HIGH;
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if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
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intel_dp->DP |= DP_SYNC_VS_HIGH;
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intel_dp->DP |= DP_LINK_TRAIN_OFF;
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if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
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intel_dp->DP |= DP_ENHANCED_FRAMING;
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if (IS_CHERRYVIEW(dev_priv))
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intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
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else
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intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
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}
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}
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static void assert_dp_port(struct intel_dp *intel_dp, bool state)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
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bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
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I915_STATE_WARN(cur_state != state,
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"[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
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dig_port->base.base.base.id, dig_port->base.base.name,
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onoff(state), onoff(cur_state));
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}
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#define assert_dp_port_disabled(d) assert_dp_port((d), false)
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static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
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{
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bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
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I915_STATE_WARN(cur_state != state,
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"eDP PLL state assertion failure (expected %s, current %s)\n",
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onoff(state), onoff(cur_state));
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}
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#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
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#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
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static void ilk_edp_pll_on(struct intel_dp *intel_dp,
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const struct intel_crtc_state *pipe_config)
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{
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
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assert_dp_port_disabled(intel_dp);
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assert_edp_pll_disabled(dev_priv);
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drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
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pipe_config->port_clock);
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intel_dp->DP &= ~DP_PLL_FREQ_MASK;
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if (pipe_config->port_clock == 162000)
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intel_dp->DP |= DP_PLL_FREQ_162MHZ;
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else
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intel_dp->DP |= DP_PLL_FREQ_270MHZ;
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intel_de_write(dev_priv, DP_A, intel_dp->DP);
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intel_de_posting_read(dev_priv, DP_A);
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udelay(500);
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/*
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* [DevILK] Work around required when enabling DP PLL
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* while a pipe is enabled going to FDI:
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* 1. Wait for the start of vertical blank on the enabled pipe going to FDI
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* 2. Program DP PLL enable
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*/
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if (IS_IRONLAKE(dev_priv))
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intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
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intel_dp->DP |= DP_PLL_ENABLE;
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intel_de_write(dev_priv, DP_A, intel_dp->DP);
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intel_de_posting_read(dev_priv, DP_A);
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udelay(200);
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}
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static void ilk_edp_pll_off(struct intel_dp *intel_dp,
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const struct intel_crtc_state *old_crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
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assert_dp_port_disabled(intel_dp);
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assert_edp_pll_enabled(dev_priv);
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drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
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intel_dp->DP &= ~DP_PLL_ENABLE;
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intel_de_write(dev_priv, DP_A, intel_dp->DP);
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intel_de_posting_read(dev_priv, DP_A);
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udelay(200);
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}
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static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
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enum port port, enum pipe *pipe)
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{
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enum pipe p;
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for_each_pipe(dev_priv, p) {
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u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
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if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
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*pipe = p;
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return true;
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}
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}
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drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
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port_name(port));
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/* must initialize pipe to something for the asserts */
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*pipe = PIPE_A;
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return false;
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}
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bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv,
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i915_reg_t dp_reg, enum port port,
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enum pipe *pipe)
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{
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bool ret;
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u32 val;
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val = intel_de_read(dev_priv, dp_reg);
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ret = val & DP_PORT_EN;
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/* asserts want to know the pipe even if the port is disabled */
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if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
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*pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
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else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
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ret &= cpt_dp_port_selected(dev_priv, port, pipe);
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else if (IS_CHERRYVIEW(dev_priv))
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*pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
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else
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*pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
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return ret;
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}
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static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
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enum pipe *pipe)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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intel_wakeref_t wakeref;
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bool ret;
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wakeref = intel_display_power_get_if_enabled(dev_priv,
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encoder->power_domain);
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if (!wakeref)
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return false;
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ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
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encoder->port, pipe);
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intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
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return ret;
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}
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static void intel_dp_get_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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u32 tmp, flags = 0;
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enum port port = encoder->port;
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
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if (encoder->type == INTEL_OUTPUT_EDP)
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pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
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else
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pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
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tmp = intel_de_read(dev_priv, intel_dp->output_reg);
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pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
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if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
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u32 trans_dp = intel_de_read(dev_priv,
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TRANS_DP_CTL(crtc->pipe));
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if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
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flags |= DRM_MODE_FLAG_PHSYNC;
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else
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flags |= DRM_MODE_FLAG_NHSYNC;
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if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
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flags |= DRM_MODE_FLAG_PVSYNC;
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else
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flags |= DRM_MODE_FLAG_NVSYNC;
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} else {
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if (tmp & DP_SYNC_HS_HIGH)
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flags |= DRM_MODE_FLAG_PHSYNC;
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else
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flags |= DRM_MODE_FLAG_NHSYNC;
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if (tmp & DP_SYNC_VS_HIGH)
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flags |= DRM_MODE_FLAG_PVSYNC;
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else
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flags |= DRM_MODE_FLAG_NVSYNC;
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}
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pipe_config->hw.adjusted_mode.flags |= flags;
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if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
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pipe_config->limited_color_range = true;
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pipe_config->lane_count =
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((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
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intel_dp_get_m_n(crtc, pipe_config);
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if (port == PORT_A) {
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if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
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pipe_config->port_clock = 162000;
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else
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pipe_config->port_clock = 270000;
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}
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pipe_config->hw.adjusted_mode.crtc_clock =
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intel_dotclock_calculate(pipe_config->port_clock,
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&pipe_config->dp_m_n);
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if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
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pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
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/*
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* This is a big fat ugly hack.
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*
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* Some machines in UEFI boot mode provide us a VBT that has 18
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* bpp and 1.62 GHz link bandwidth for eDP, which for reasons
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* unknown we fail to light up. Yet the same BIOS boots up with
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* 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
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* max, not what it tells us to use.
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*
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* Note: This will still be broken if the eDP panel is not lit
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* up by the BIOS, and thus we can't get the mode at module
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* load.
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*/
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drm_dbg_kms(&dev_priv->drm,
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"pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
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pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
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dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
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}
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}
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static void
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intel_dp_link_down(struct intel_encoder *encoder,
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const struct intel_crtc_state *old_crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
|
|
enum port port = encoder->port;
|
|
u32 DP = intel_dp->DP;
|
|
|
|
if (drm_WARN_ON(&dev_priv->drm,
|
|
(intel_de_read(dev_priv, intel_dp->output_reg) &
|
|
DP_PORT_EN) == 0))
|
|
return;
|
|
|
|
drm_dbg_kms(&dev_priv->drm, "\n");
|
|
|
|
if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
|
|
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
|
|
DP &= ~DP_LINK_TRAIN_MASK_CPT;
|
|
DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
|
|
} else {
|
|
DP &= ~DP_LINK_TRAIN_MASK;
|
|
DP |= DP_LINK_TRAIN_PAT_IDLE;
|
|
}
|
|
intel_de_write(dev_priv, intel_dp->output_reg, DP);
|
|
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
|
|
|
DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
|
|
intel_de_write(dev_priv, intel_dp->output_reg, DP);
|
|
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
|
|
|
/*
|
|
* HW workaround for IBX, we need to move the port
|
|
* to transcoder A after disabling it to allow the
|
|
* matching HDMI port to be enabled on transcoder A.
|
|
*/
|
|
if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
|
|
/*
|
|
* We get CPU/PCH FIFO underruns on the other pipe when
|
|
* doing the workaround. Sweep them under the rug.
|
|
*/
|
|
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
|
|
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
|
|
|
|
/* always enable with pattern 1 (as per spec) */
|
|
DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
|
|
DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
|
|
DP_LINK_TRAIN_PAT_1;
|
|
intel_de_write(dev_priv, intel_dp->output_reg, DP);
|
|
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
|
|
|
DP &= ~DP_PORT_EN;
|
|
intel_de_write(dev_priv, intel_dp->output_reg, DP);
|
|
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
|
|
|
intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
|
|
intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
|
|
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
|
|
}
|
|
|
|
msleep(intel_dp->pps.panel_power_down_delay);
|
|
|
|
intel_dp->DP = DP;
|
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
|
intel_wakeref_t wakeref;
|
|
|
|
with_intel_pps_lock(intel_dp, wakeref)
|
|
intel_dp->pps.active_pipe = INVALID_PIPE;
|
|
}
|
|
}
|
|
|
|
static void intel_disable_dp(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
const struct drm_connector_state *old_conn_state)
|
|
{
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
|
|
intel_dp->link_trained = false;
|
|
|
|
if (old_crtc_state->has_audio)
|
|
intel_audio_codec_disable(encoder,
|
|
old_crtc_state, old_conn_state);
|
|
|
|
/*
|
|
* Make sure the panel is off before trying to change the mode.
|
|
* But also ensure that we have vdd while we switch off the panel.
|
|
*/
|
|
intel_pps_vdd_on(intel_dp);
|
|
intel_edp_backlight_off(old_conn_state);
|
|
intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
|
|
intel_pps_off(intel_dp);
|
|
}
|
|
|
|
static void g4x_disable_dp(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
const struct drm_connector_state *old_conn_state)
|
|
{
|
|
intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
|
|
}
|
|
|
|
static void vlv_disable_dp(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
const struct drm_connector_state *old_conn_state)
|
|
{
|
|
intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
|
|
}
|
|
|
|
static void g4x_post_disable_dp(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
const struct drm_connector_state *old_conn_state)
|
|
{
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
enum port port = encoder->port;
|
|
|
|
/*
|
|
* Bspec does not list a specific disable sequence for g4x DP.
|
|
* Follow the ilk+ sequence (disable pipe before the port) for
|
|
* g4x DP as it does not suffer from underruns like the normal
|
|
* g4x modeset sequence (disable pipe after the port).
|
|
*/
|
|
intel_dp_link_down(encoder, old_crtc_state);
|
|
|
|
/* Only ilk+ has port A */
|
|
if (port == PORT_A)
|
|
ilk_edp_pll_off(intel_dp, old_crtc_state);
|
|
}
|
|
|
|
static void vlv_post_disable_dp(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
const struct drm_connector_state *old_conn_state)
|
|
{
|
|
intel_dp_link_down(encoder, old_crtc_state);
|
|
}
|
|
|
|
static void chv_post_disable_dp(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
const struct drm_connector_state *old_conn_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
intel_dp_link_down(encoder, old_crtc_state);
|
|
|
|
vlv_dpio_get(dev_priv);
|
|
|
|
/* Assert data lane reset */
|
|
chv_data_lane_soft_reset(encoder, old_crtc_state, true);
|
|
|
|
vlv_dpio_put(dev_priv);
|
|
}
|
|
|
|
static void
|
|
cpt_set_link_train(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state,
|
|
u8 dp_train_pat)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
u32 *DP = &intel_dp->DP;
|
|
|
|
*DP &= ~DP_LINK_TRAIN_MASK_CPT;
|
|
|
|
switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
|
|
case DP_TRAINING_PATTERN_DISABLE:
|
|
*DP |= DP_LINK_TRAIN_OFF_CPT;
|
|
break;
|
|
case DP_TRAINING_PATTERN_1:
|
|
*DP |= DP_LINK_TRAIN_PAT_1_CPT;
|
|
break;
|
|
case DP_TRAINING_PATTERN_2:
|
|
*DP |= DP_LINK_TRAIN_PAT_2_CPT;
|
|
break;
|
|
default:
|
|
MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
|
|
return;
|
|
}
|
|
|
|
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
|
|
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
|
}
|
|
|
|
static void
|
|
g4x_set_link_train(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state,
|
|
u8 dp_train_pat)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
u32 *DP = &intel_dp->DP;
|
|
|
|
*DP &= ~DP_LINK_TRAIN_MASK;
|
|
|
|
switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
|
|
case DP_TRAINING_PATTERN_DISABLE:
|
|
*DP |= DP_LINK_TRAIN_OFF;
|
|
break;
|
|
case DP_TRAINING_PATTERN_1:
|
|
*DP |= DP_LINK_TRAIN_PAT_1;
|
|
break;
|
|
case DP_TRAINING_PATTERN_2:
|
|
*DP |= DP_LINK_TRAIN_PAT_2;
|
|
break;
|
|
default:
|
|
MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
|
|
return;
|
|
}
|
|
|
|
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
|
|
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
|
}
|
|
|
|
static void intel_dp_enable_port(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
|
|
/* enable with pattern 1 (as per spec) */
|
|
|
|
intel_dp_program_link_training_pattern(intel_dp, crtc_state,
|
|
DP_TRAINING_PATTERN_1);
|
|
|
|
/*
|
|
* Magic for VLV/CHV. We _must_ first set up the register
|
|
* without actually enabling the port, and then do another
|
|
* write to enable the port. Otherwise link training will
|
|
* fail when the power sequencer is freshly used for this port.
|
|
*/
|
|
intel_dp->DP |= DP_PORT_EN;
|
|
if (crtc_state->has_audio)
|
|
intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
|
|
|
|
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
|
|
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
|
}
|
|
|
|
static void intel_enable_dp(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *pipe_config,
|
|
const struct drm_connector_state *conn_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
|
|
u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
|
|
enum pipe pipe = crtc->pipe;
|
|
intel_wakeref_t wakeref;
|
|
|
|
if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
|
|
return;
|
|
|
|
with_intel_pps_lock(intel_dp, wakeref) {
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
|
|
vlv_pps_init(encoder, pipe_config);
|
|
|
|
intel_dp_enable_port(intel_dp, pipe_config);
|
|
|
|
intel_pps_vdd_on_unlocked(intel_dp);
|
|
intel_pps_on_unlocked(intel_dp);
|
|
intel_pps_vdd_off_unlocked(intel_dp, true);
|
|
}
|
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
|
unsigned int lane_mask = 0x0;
|
|
|
|
if (IS_CHERRYVIEW(dev_priv))
|
|
lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
|
|
|
|
vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
|
|
lane_mask);
|
|
}
|
|
|
|
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
|
|
intel_dp_configure_protocol_converter(intel_dp, pipe_config);
|
|
intel_dp_check_frl_training(intel_dp);
|
|
intel_dp_pcon_dsc_configure(intel_dp, pipe_config);
|
|
intel_dp_start_link_train(intel_dp, pipe_config);
|
|
intel_dp_stop_link_train(intel_dp, pipe_config);
|
|
|
|
if (pipe_config->has_audio) {
|
|
drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
|
|
pipe_name(pipe));
|
|
intel_audio_codec_enable(encoder, pipe_config, conn_state);
|
|
}
|
|
}
|
|
|
|
static void g4x_enable_dp(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *pipe_config,
|
|
const struct drm_connector_state *conn_state)
|
|
{
|
|
intel_enable_dp(state, encoder, pipe_config, conn_state);
|
|
intel_edp_backlight_on(pipe_config, conn_state);
|
|
}
|
|
|
|
static void vlv_enable_dp(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *pipe_config,
|
|
const struct drm_connector_state *conn_state)
|
|
{
|
|
intel_edp_backlight_on(pipe_config, conn_state);
|
|
}
|
|
|
|
static void g4x_pre_enable_dp(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *pipe_config,
|
|
const struct drm_connector_state *conn_state)
|
|
{
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
enum port port = encoder->port;
|
|
|
|
intel_dp_prepare(encoder, pipe_config);
|
|
|
|
/* Only ilk+ has port A */
|
|
if (port == PORT_A)
|
|
ilk_edp_pll_on(intel_dp, pipe_config);
|
|
}
|
|
|
|
static void vlv_pre_enable_dp(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *pipe_config,
|
|
const struct drm_connector_state *conn_state)
|
|
{
|
|
vlv_phy_pre_encoder_enable(encoder, pipe_config);
|
|
|
|
intel_enable_dp(state, encoder, pipe_config, conn_state);
|
|
}
|
|
|
|
static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *pipe_config,
|
|
const struct drm_connector_state *conn_state)
|
|
{
|
|
intel_dp_prepare(encoder, pipe_config);
|
|
|
|
vlv_phy_pre_pll_enable(encoder, pipe_config);
|
|
}
|
|
|
|
static void chv_pre_enable_dp(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *pipe_config,
|
|
const struct drm_connector_state *conn_state)
|
|
{
|
|
chv_phy_pre_encoder_enable(encoder, pipe_config);
|
|
|
|
intel_enable_dp(state, encoder, pipe_config, conn_state);
|
|
|
|
/* Second common lane will stay alive on its own now */
|
|
chv_phy_release_cl2_override(encoder);
|
|
}
|
|
|
|
static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *pipe_config,
|
|
const struct drm_connector_state *conn_state)
|
|
{
|
|
intel_dp_prepare(encoder, pipe_config);
|
|
|
|
chv_phy_pre_pll_enable(encoder, pipe_config);
|
|
}
|
|
|
|
static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *old_crtc_state,
|
|
const struct drm_connector_state *old_conn_state)
|
|
{
|
|
chv_phy_post_pll_disable(encoder, old_crtc_state);
|
|
}
|
|
|
|
static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
|
|
}
|
|
|
|
static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
|
|
}
|
|
|
|
static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
|
|
{
|
|
return DP_TRAIN_PRE_EMPH_LEVEL_2;
|
|
}
|
|
|
|
static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
|
|
{
|
|
return DP_TRAIN_PRE_EMPH_LEVEL_3;
|
|
}
|
|
|
|
static void vlv_set_signal_levels(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
|
|
unsigned long demph_reg_value, preemph_reg_value,
|
|
uniqtranscale_reg_value;
|
|
u8 train_set = intel_dp->train_set[0];
|
|
|
|
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
|
|
case DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
preemph_reg_value = 0x0004000;
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
|
|
demph_reg_value = 0x2B405555;
|
|
uniqtranscale_reg_value = 0x552AB83A;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
|
|
demph_reg_value = 0x2B404040;
|
|
uniqtranscale_reg_value = 0x5548B83A;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
|
|
demph_reg_value = 0x2B245555;
|
|
uniqtranscale_reg_value = 0x5560B83A;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
|
|
demph_reg_value = 0x2B405555;
|
|
uniqtranscale_reg_value = 0x5598DA3A;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
break;
|
|
case DP_TRAIN_PRE_EMPH_LEVEL_1:
|
|
preemph_reg_value = 0x0002000;
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
|
|
demph_reg_value = 0x2B404040;
|
|
uniqtranscale_reg_value = 0x5552B83A;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
|
|
demph_reg_value = 0x2B404848;
|
|
uniqtranscale_reg_value = 0x5580B83A;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
|
|
demph_reg_value = 0x2B404040;
|
|
uniqtranscale_reg_value = 0x55ADDA3A;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
break;
|
|
case DP_TRAIN_PRE_EMPH_LEVEL_2:
|
|
preemph_reg_value = 0x0000000;
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
|
|
demph_reg_value = 0x2B305555;
|
|
uniqtranscale_reg_value = 0x5570B83A;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
|
|
demph_reg_value = 0x2B2B4040;
|
|
uniqtranscale_reg_value = 0x55ADDA3A;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
break;
|
|
case DP_TRAIN_PRE_EMPH_LEVEL_3:
|
|
preemph_reg_value = 0x0006000;
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
|
|
demph_reg_value = 0x1B405555;
|
|
uniqtranscale_reg_value = 0x55ADDA3A;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
vlv_set_phy_signal_level(encoder, crtc_state,
|
|
demph_reg_value, preemph_reg_value,
|
|
uniqtranscale_reg_value, 0);
|
|
}
|
|
|
|
static void chv_set_signal_levels(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
|
|
u32 deemph_reg_value, margin_reg_value;
|
|
bool uniq_trans_scale = false;
|
|
u8 train_set = intel_dp->train_set[0];
|
|
|
|
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
|
|
case DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
|
|
deemph_reg_value = 128;
|
|
margin_reg_value = 52;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
|
|
deemph_reg_value = 128;
|
|
margin_reg_value = 77;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
|
|
deemph_reg_value = 128;
|
|
margin_reg_value = 102;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
|
|
deemph_reg_value = 128;
|
|
margin_reg_value = 154;
|
|
uniq_trans_scale = true;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
break;
|
|
case DP_TRAIN_PRE_EMPH_LEVEL_1:
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
|
|
deemph_reg_value = 85;
|
|
margin_reg_value = 78;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
|
|
deemph_reg_value = 85;
|
|
margin_reg_value = 116;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
|
|
deemph_reg_value = 85;
|
|
margin_reg_value = 154;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
break;
|
|
case DP_TRAIN_PRE_EMPH_LEVEL_2:
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
|
|
deemph_reg_value = 64;
|
|
margin_reg_value = 104;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
|
|
deemph_reg_value = 64;
|
|
margin_reg_value = 154;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
break;
|
|
case DP_TRAIN_PRE_EMPH_LEVEL_3:
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
|
|
deemph_reg_value = 43;
|
|
margin_reg_value = 154;
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
chv_set_phy_signal_level(encoder, crtc_state,
|
|
deemph_reg_value, margin_reg_value,
|
|
uniq_trans_scale);
|
|
}
|
|
|
|
static u32 g4x_signal_levels(u8 train_set)
|
|
{
|
|
u32 signal_levels = 0;
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
|
|
default:
|
|
signal_levels |= DP_VOLTAGE_0_4;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
|
|
signal_levels |= DP_VOLTAGE_0_6;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
|
|
signal_levels |= DP_VOLTAGE_0_8;
|
|
break;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
|
|
signal_levels |= DP_VOLTAGE_1_2;
|
|
break;
|
|
}
|
|
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
|
|
case DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
default:
|
|
signal_levels |= DP_PRE_EMPHASIS_0;
|
|
break;
|
|
case DP_TRAIN_PRE_EMPH_LEVEL_1:
|
|
signal_levels |= DP_PRE_EMPHASIS_3_5;
|
|
break;
|
|
case DP_TRAIN_PRE_EMPH_LEVEL_2:
|
|
signal_levels |= DP_PRE_EMPHASIS_6;
|
|
break;
|
|
case DP_TRAIN_PRE_EMPH_LEVEL_3:
|
|
signal_levels |= DP_PRE_EMPHASIS_9_5;
|
|
break;
|
|
}
|
|
return signal_levels;
|
|
}
|
|
|
|
static void
|
|
g4x_set_signal_levels(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
u8 train_set = intel_dp->train_set[0];
|
|
u32 signal_levels;
|
|
|
|
signal_levels = g4x_signal_levels(train_set);
|
|
|
|
drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
|
|
signal_levels);
|
|
|
|
intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
|
|
intel_dp->DP |= signal_levels;
|
|
|
|
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
|
|
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
|
}
|
|
|
|
/* SNB CPU eDP voltage swing and pre-emphasis control */
|
|
static u32 snb_cpu_edp_signal_levels(u8 train_set)
|
|
{
|
|
u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
|
|
DP_TRAIN_PRE_EMPHASIS_MASK);
|
|
|
|
switch (signal_levels) {
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
|
|
return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
|
|
return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
|
|
return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
|
|
default:
|
|
MISSING_CASE(signal_levels);
|
|
return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
|
|
}
|
|
}
|
|
|
|
static void
|
|
snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
u8 train_set = intel_dp->train_set[0];
|
|
u32 signal_levels;
|
|
|
|
signal_levels = snb_cpu_edp_signal_levels(train_set);
|
|
|
|
drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
|
|
signal_levels);
|
|
|
|
intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
|
|
intel_dp->DP |= signal_levels;
|
|
|
|
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
|
|
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
|
}
|
|
|
|
/* IVB CPU eDP voltage swing and pre-emphasis control */
|
|
static u32 ivb_cpu_edp_signal_levels(u8 train_set)
|
|
{
|
|
u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
|
|
DP_TRAIN_PRE_EMPHASIS_MASK);
|
|
|
|
switch (signal_levels) {
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
return EDP_LINK_TRAIN_400MV_0DB_IVB;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
|
|
return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
|
|
return EDP_LINK_TRAIN_400MV_6DB_IVB;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
return EDP_LINK_TRAIN_600MV_0DB_IVB;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
|
|
return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
|
|
return EDP_LINK_TRAIN_800MV_0DB_IVB;
|
|
case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
|
|
return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
|
|
|
|
default:
|
|
MISSING_CASE(signal_levels);
|
|
return EDP_LINK_TRAIN_500MV_0DB_IVB;
|
|
}
|
|
}
|
|
|
|
static void
|
|
ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
u8 train_set = intel_dp->train_set[0];
|
|
u32 signal_levels;
|
|
|
|
signal_levels = ivb_cpu_edp_signal_levels(train_set);
|
|
|
|
drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
|
|
signal_levels);
|
|
|
|
intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
|
|
intel_dp->DP |= signal_levels;
|
|
|
|
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
|
|
intel_de_posting_read(dev_priv, intel_dp->output_reg);
|
|
}
|
|
|
|
/*
|
|
* If display is now connected check links status,
|
|
* there has been known issues of link loss triggering
|
|
* long pulse.
|
|
*
|
|
* Some sinks (eg. ASUS PB287Q) seem to perform some
|
|
* weird HPD ping pong during modesets. So we can apparently
|
|
* end up with HPD going low during a modeset, and then
|
|
* going back up soon after. And once that happens we must
|
|
* retrain the link to get a picture. That's in case no
|
|
* userspace component reacted to intermittent HPD dip.
|
|
*/
|
|
static enum intel_hotplug_state
|
|
intel_dp_hotplug(struct intel_encoder *encoder,
|
|
struct intel_connector *connector)
|
|
{
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
|
|
struct drm_modeset_acquire_ctx ctx;
|
|
enum intel_hotplug_state state;
|
|
int ret;
|
|
|
|
if (intel_dp->compliance.test_active &&
|
|
intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
|
|
intel_dp_phy_test(encoder);
|
|
/* just do the PHY test and nothing else */
|
|
return INTEL_HOTPLUG_UNCHANGED;
|
|
}
|
|
|
|
state = intel_encoder_hotplug(encoder, connector);
|
|
|
|
drm_modeset_acquire_init(&ctx, 0);
|
|
|
|
for (;;) {
|
|
ret = intel_dp_retrain_link(encoder, &ctx);
|
|
|
|
if (ret == -EDEADLK) {
|
|
drm_modeset_backoff(&ctx);
|
|
continue;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
drm_modeset_drop_locks(&ctx);
|
|
drm_modeset_acquire_fini(&ctx);
|
|
drm_WARN(encoder->base.dev, ret,
|
|
"Acquiring modeset locks failed with %i\n", ret);
|
|
|
|
/*
|
|
* Keeping it consistent with intel_ddi_hotplug() and
|
|
* intel_hdmi_hotplug().
|
|
*/
|
|
if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
|
|
state = INTEL_HOTPLUG_RETRY;
|
|
|
|
return state;
|
|
}
|
|
|
|
static bool ibx_digital_port_connected(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
|
|
|
|
return intel_de_read(dev_priv, SDEISR) & bit;
|
|
}
|
|
|
|
static bool g4x_digital_port_connected(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
u32 bit;
|
|
|
|
switch (encoder->hpd_pin) {
|
|
case HPD_PORT_B:
|
|
bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
|
|
break;
|
|
case HPD_PORT_C:
|
|
bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
|
|
break;
|
|
case HPD_PORT_D:
|
|
bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
|
|
break;
|
|
default:
|
|
MISSING_CASE(encoder->hpd_pin);
|
|
return false;
|
|
}
|
|
|
|
return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
|
|
}
|
|
|
|
static bool gm45_digital_port_connected(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
u32 bit;
|
|
|
|
switch (encoder->hpd_pin) {
|
|
case HPD_PORT_B:
|
|
bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
|
|
break;
|
|
case HPD_PORT_C:
|
|
bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
|
|
break;
|
|
case HPD_PORT_D:
|
|
bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
|
|
break;
|
|
default:
|
|
MISSING_CASE(encoder->hpd_pin);
|
|
return false;
|
|
}
|
|
|
|
return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
|
|
}
|
|
|
|
static bool ilk_digital_port_connected(struct intel_encoder *encoder)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
|
|
|
|
return intel_de_read(dev_priv, DEISR) & bit;
|
|
}
|
|
|
|
static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
|
|
{
|
|
intel_dp_encoder_flush_work(encoder);
|
|
|
|
drm_encoder_cleanup(encoder);
|
|
kfree(enc_to_dig_port(to_intel_encoder(encoder)));
|
|
}
|
|
|
|
enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
|
|
enum pipe pipe;
|
|
|
|
if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,
|
|
encoder->port, &pipe))
|
|
return pipe;
|
|
|
|
return INVALID_PIPE;
|
|
}
|
|
|
|
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
|
|
|
|
intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
|
|
|
|
intel_dp->reset_link_params = true;
|
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
|
|
intel_wakeref_t wakeref;
|
|
|
|
with_intel_pps_lock(intel_dp, wakeref)
|
|
intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
|
|
}
|
|
|
|
intel_pps_encoder_reset(intel_dp);
|
|
}
|
|
|
|
static const struct drm_encoder_funcs intel_dp_enc_funcs = {
|
|
.reset = intel_dp_encoder_reset,
|
|
.destroy = intel_dp_encoder_destroy,
|
|
};
|
|
|
|
bool g4x_dp_init(struct drm_i915_private *dev_priv,
|
|
i915_reg_t output_reg, enum port port)
|
|
{
|
|
struct intel_digital_port *dig_port;
|
|
struct intel_encoder *intel_encoder;
|
|
struct drm_encoder *encoder;
|
|
struct intel_connector *intel_connector;
|
|
|
|
dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
|
|
if (!dig_port)
|
|
return false;
|
|
|
|
intel_connector = intel_connector_alloc();
|
|
if (!intel_connector)
|
|
goto err_connector_alloc;
|
|
|
|
intel_encoder = &dig_port->base;
|
|
encoder = &intel_encoder->base;
|
|
|
|
mutex_init(&dig_port->hdcp_mutex);
|
|
|
|
if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
|
|
&intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
|
|
"DP %c", port_name(port)))
|
|
goto err_encoder_init;
|
|
|
|
intel_encoder->hotplug = intel_dp_hotplug;
|
|
intel_encoder->compute_config = intel_dp_compute_config;
|
|
intel_encoder->get_hw_state = intel_dp_get_hw_state;
|
|
intel_encoder->get_config = intel_dp_get_config;
|
|
intel_encoder->sync_state = intel_dp_sync_state;
|
|
intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
|
|
intel_encoder->update_pipe = intel_panel_update_backlight;
|
|
intel_encoder->suspend = intel_dp_encoder_suspend;
|
|
intel_encoder->shutdown = intel_dp_encoder_shutdown;
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
|
intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
|
|
intel_encoder->pre_enable = chv_pre_enable_dp;
|
|
intel_encoder->enable = vlv_enable_dp;
|
|
intel_encoder->disable = vlv_disable_dp;
|
|
intel_encoder->post_disable = chv_post_disable_dp;
|
|
intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
|
|
} else if (IS_VALLEYVIEW(dev_priv)) {
|
|
intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
|
|
intel_encoder->pre_enable = vlv_pre_enable_dp;
|
|
intel_encoder->enable = vlv_enable_dp;
|
|
intel_encoder->disable = vlv_disable_dp;
|
|
intel_encoder->post_disable = vlv_post_disable_dp;
|
|
} else {
|
|
intel_encoder->pre_enable = g4x_pre_enable_dp;
|
|
intel_encoder->enable = g4x_enable_dp;
|
|
intel_encoder->disable = g4x_disable_dp;
|
|
intel_encoder->post_disable = g4x_post_disable_dp;
|
|
}
|
|
|
|
if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
|
|
(HAS_PCH_CPT(dev_priv) && port != PORT_A))
|
|
dig_port->dp.set_link_train = cpt_set_link_train;
|
|
else
|
|
dig_port->dp.set_link_train = g4x_set_link_train;
|
|
|
|
if (IS_CHERRYVIEW(dev_priv))
|
|
dig_port->dp.set_signal_levels = chv_set_signal_levels;
|
|
else if (IS_VALLEYVIEW(dev_priv))
|
|
dig_port->dp.set_signal_levels = vlv_set_signal_levels;
|
|
else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
|
|
dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;
|
|
else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)
|
|
dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;
|
|
else
|
|
dig_port->dp.set_signal_levels = g4x_set_signal_levels;
|
|
|
|
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
|
|
(HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
|
|
dig_port->dp.preemph_max = intel_dp_preemph_max_3;
|
|
dig_port->dp.voltage_max = intel_dp_voltage_max_3;
|
|
} else {
|
|
dig_port->dp.preemph_max = intel_dp_preemph_max_2;
|
|
dig_port->dp.voltage_max = intel_dp_voltage_max_2;
|
|
}
|
|
|
|
dig_port->dp.output_reg = output_reg;
|
|
dig_port->max_lanes = 4;
|
|
|
|
intel_encoder->type = INTEL_OUTPUT_DP;
|
|
intel_encoder->power_domain = intel_port_to_power_domain(port);
|
|
if (IS_CHERRYVIEW(dev_priv)) {
|
|
if (port == PORT_D)
|
|
intel_encoder->pipe_mask = BIT(PIPE_C);
|
|
else
|
|
intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
|
|
} else {
|
|
intel_encoder->pipe_mask = ~0;
|
|
}
|
|
intel_encoder->cloneable = 0;
|
|
intel_encoder->port = port;
|
|
intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
|
|
|
|
dig_port->hpd_pulse = intel_dp_hpd_pulse;
|
|
|
|
if (HAS_GMCH(dev_priv)) {
|
|
if (IS_GM45(dev_priv))
|
|
dig_port->connected = gm45_digital_port_connected;
|
|
else
|
|
dig_port->connected = g4x_digital_port_connected;
|
|
} else {
|
|
if (port == PORT_A)
|
|
dig_port->connected = ilk_digital_port_connected;
|
|
else
|
|
dig_port->connected = ibx_digital_port_connected;
|
|
}
|
|
|
|
if (port != PORT_A)
|
|
intel_infoframe_init(dig_port);
|
|
|
|
dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
|
|
if (!intel_dp_init_connector(dig_port, intel_connector))
|
|
goto err_init_connector;
|
|
|
|
return true;
|
|
|
|
err_init_connector:
|
|
drm_encoder_cleanup(encoder);
|
|
err_encoder_init:
|
|
kfree(intel_connector);
|
|
err_connector_alloc:
|
|
kfree(dig_port);
|
|
return false;
|
|
}
|