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dc98f50fa5
Since we now have proper old and new cdclk state we no longer need to keep this flag to indicate that the force min cdclk has changed. Instead just check if the old vs. new value are different. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200714152626.380-4-ville.syrjala@linux.intel.com Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
83 lines
2.6 KiB
C
83 lines
2.6 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_CDCLK_H__
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#define __INTEL_CDCLK_H__
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#include <linux/types.h>
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#include "i915_drv.h"
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#include "intel_display.h"
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#include "intel_global_state.h"
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struct drm_i915_private;
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struct intel_atomic_state;
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struct intel_crtc_state;
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struct intel_cdclk_vals {
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u32 cdclk;
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u16 refclk;
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u8 divider; /* CD2X divider * 2 */
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u8 ratio;
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};
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struct intel_cdclk_state {
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struct intel_global_state base;
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/*
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* Logical configuration of cdclk (used for all scaling,
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* watermark, etc. calculations and checks). This is
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* computed as if all enabled crtcs were active.
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*/
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struct intel_cdclk_config logical;
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/*
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* Actual configuration of cdclk, can be different from the
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* logical configuration only when all crtc's are DPMS off.
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*/
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struct intel_cdclk_config actual;
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/* minimum acceptable cdclk for each pipe */
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int min_cdclk[I915_MAX_PIPES];
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/* minimum acceptable voltage level for each pipe */
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u8 min_voltage_level[I915_MAX_PIPES];
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/* pipe to which cd2x update is synchronized */
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enum pipe pipe;
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/* forced minimum cdclk for glk+ audio w/a */
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int force_min_cdclk;
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/* bitmask of active pipes */
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u8 active_pipes;
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};
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int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
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void intel_cdclk_init_hw(struct drm_i915_private *i915);
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void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
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void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
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void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
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void intel_update_cdclk(struct drm_i915_private *dev_priv);
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u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
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bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
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const struct intel_cdclk_config *b);
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void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
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void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
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void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
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const char *context);
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int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
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struct intel_cdclk_state *
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intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
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#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
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#define intel_atomic_get_old_cdclk_state(state) \
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to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
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#define intel_atomic_get_new_cdclk_state(state) \
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to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
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int intel_cdclk_init(struct drm_i915_private *dev_priv);
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#endif /* __INTEL_CDCLK_H__ */
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