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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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fcf83a2114
We lost the i915_reg_rw tracepoint for a lot of display registers
when we switched from the heavyweight normal register accessors to
the lightweight _fw() variants. See eg. commit dd584fc071
("drm/i915: Use I915_READ_FW for plane updates").
Put the tracepoints back so that the register traces might
actually be useful. Hopefully these should be close to free
when the tracepoint is not enabled and thus not slow down
our vblank critical sections significantly.
v2: Copy paste the same-cacheline-hang warning from
intel_uncore.h (Anshuman)
Cc: Cooper Chiou <cooper.chiou@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210430143945.6776-2-ville.syrjala@linux.intel.com
85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DE_H__
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#define __INTEL_DE_H__
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "i915_trace.h"
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#include "intel_uncore.h"
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static inline u32
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intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
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{
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return intel_uncore_read(&i915->uncore, reg);
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}
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static inline void
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intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
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{
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intel_uncore_posting_read(&i915->uncore, reg);
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}
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static inline void
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intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
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{
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intel_uncore_write(&i915->uncore, reg, val);
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}
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static inline void
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intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
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{
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intel_uncore_rmw(&i915->uncore, reg, clear, set);
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}
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static inline int
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intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout)
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{
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return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);
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}
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static inline int
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intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, unsigned int timeout)
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{
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return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
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}
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static inline int
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intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
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u32 mask, unsigned int timeout)
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{
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return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
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}
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/*
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* Unlocked mmio-accessors, think carefully before using these.
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*
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* Certain architectures will die if the same cacheline is concurrently accessed
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* by different clients (e.g. on Ivybridge). Access to registers should
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* therefore generally be serialised, by either the dev_priv->uncore.lock or
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* a more localised lock guarding all access to that bank of registers.
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*/
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static inline u32
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intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
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{
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u32 val;
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val = intel_uncore_read_fw(&i915->uncore, reg);
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trace_i915_reg_rw(false, reg, val, sizeof(val), true);
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return val;
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}
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static inline void
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intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
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{
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trace_i915_reg_rw(true, reg, val, sizeof(val), true);
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intel_uncore_write_fw(&i915->uncore, reg, val);
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}
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#endif /* __INTEL_DE_H__ */
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