mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
![Jani Nikula](/assets/img/avatar_default.png)
DP 2.0 UHBR link rates always use 128b/132b channel encoding, which has a different data bandwidth efficiency from 8b/10b. The computation is slightly convoluted due to the units we use; this is all explained in the added comment. v2: Clarified comment (Manasi) Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/8afd8d97a04c2d86c2dcadfed9f8e1f84272a13c.1629735412.git.jani.nikula@intel.com
132 lines
5.3 KiB
C
132 lines
5.3 KiB
C
/* SPDX-License-Identifier: MIT */
|
|
/*
|
|
* Copyright © 2019 Intel Corporation
|
|
*/
|
|
|
|
#ifndef __INTEL_DP_H__
|
|
#define __INTEL_DP_H__
|
|
|
|
#include <linux/types.h>
|
|
|
|
#include "i915_reg.h"
|
|
|
|
enum intel_output_format;
|
|
enum pipe;
|
|
enum port;
|
|
struct drm_connector_state;
|
|
struct drm_encoder;
|
|
struct drm_i915_private;
|
|
struct drm_modeset_acquire_ctx;
|
|
struct drm_dp_vsc_sdp;
|
|
struct intel_atomic_state;
|
|
struct intel_connector;
|
|
struct intel_crtc_state;
|
|
struct intel_digital_port;
|
|
struct intel_dp;
|
|
struct intel_encoder;
|
|
|
|
struct link_config_limits {
|
|
int min_rate, max_rate;
|
|
int min_lane_count, max_lane_count;
|
|
int min_bpp, max_bpp;
|
|
};
|
|
|
|
void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
|
|
struct intel_crtc_state *pipe_config,
|
|
struct link_config_limits *limits);
|
|
bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
|
|
const struct drm_connector_state *conn_state);
|
|
int intel_dp_min_bpp(enum intel_output_format output_format);
|
|
bool intel_dp_init_connector(struct intel_digital_port *dig_port,
|
|
struct intel_connector *intel_connector);
|
|
void intel_dp_set_link_params(struct intel_dp *intel_dp,
|
|
int link_rate, int lane_count);
|
|
int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
|
|
int link_rate, u8 lane_count);
|
|
int intel_dp_retrain_link(struct intel_encoder *encoder,
|
|
struct drm_modeset_acquire_ctx *ctx);
|
|
void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
|
|
void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state);
|
|
void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state,
|
|
bool enable);
|
|
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
|
|
void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder);
|
|
void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
|
|
int intel_dp_compute_config(struct intel_encoder *encoder,
|
|
struct intel_crtc_state *pipe_config,
|
|
struct drm_connector_state *conn_state);
|
|
bool intel_dp_is_edp(struct intel_dp *intel_dp);
|
|
bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
|
|
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
|
|
bool long_hpd);
|
|
void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
|
|
const struct drm_connector_state *conn_state);
|
|
void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
|
|
void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
|
|
void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
|
|
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
|
|
int intel_dp_max_lane_count(struct intel_dp *intel_dp);
|
|
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
|
|
|
|
void intel_edp_drrs_enable(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state);
|
|
void intel_edp_drrs_disable(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state);
|
|
void intel_edp_drrs_update(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state);
|
|
void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
|
|
unsigned int frontbuffer_bits);
|
|
void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
|
|
unsigned int frontbuffer_bits);
|
|
|
|
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
|
|
u8 *link_bw, u8 *rate_select);
|
|
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
|
|
bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
|
|
|
|
bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
|
|
int intel_dp_link_required(int pixel_clock, int bpp);
|
|
int intel_dp_max_data_rate(int max_link_rate, int max_lanes);
|
|
bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp);
|
|
bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
|
|
const struct drm_connector_state *conn_state);
|
|
void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state,
|
|
const struct drm_connector_state *conn_state,
|
|
struct drm_dp_vsc_sdp *vsc);
|
|
void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *crtc_state,
|
|
struct drm_dp_vsc_sdp *vsc);
|
|
void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
|
|
const struct intel_crtc_state *crtc_state,
|
|
const struct drm_connector_state *conn_state);
|
|
void intel_read_dp_sdp(struct intel_encoder *encoder,
|
|
struct intel_crtc_state *crtc_state,
|
|
unsigned int type);
|
|
bool intel_digital_port_connected(struct intel_encoder *encoder);
|
|
|
|
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
|
|
{
|
|
return ~((1 << lane_count) - 1) & 0xf;
|
|
}
|
|
|
|
u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
|
|
|
|
void intel_ddi_update_pipe(struct intel_atomic_state *state,
|
|
struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *crtc_state,
|
|
const struct drm_connector_state *conn_state);
|
|
|
|
bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
|
|
struct intel_crtc_state *crtc_state);
|
|
void intel_dp_sync_state(struct intel_encoder *encoder,
|
|
const struct intel_crtc_state *crtc_state);
|
|
|
|
void intel_dp_check_frl_training(struct intel_dp *intel_dp);
|
|
void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
|
|
const struct intel_crtc_state *crtc_state);
|
|
void intel_dp_phy_test(struct intel_encoder *encoder);
|
|
|
|
#endif /* __INTEL_DP_H__ */
|