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![Lucas De Marchi](/assets/img/avatar_default.png)
Cleanup remaining cases that we find CNL in the codebase. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210728215946.1573015-22-lucas.demarchi@intel.com
698 lines
18 KiB
C
698 lines
18 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020-2021 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_display_types.h"
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#include "intel_dp_aux.h"
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#include "intel_pps.h"
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#include "intel_tc.h"
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u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
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{
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int i;
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u32 v = 0;
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if (src_bytes > 4)
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src_bytes = 4;
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for (i = 0; i < src_bytes; i++)
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v |= ((u32)src[i]) << ((3 - i) * 8);
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return v;
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}
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static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
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{
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int i;
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if (dst_bytes > 4)
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dst_bytes = 4;
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for (i = 0; i < dst_bytes; i++)
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dst[i] = src >> ((3 - i) * 8);
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}
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static u32
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intel_dp_aux_wait_done(struct intel_dp *intel_dp)
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{
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
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const unsigned int timeout_ms = 10;
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u32 status;
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bool done;
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#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
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done = wait_event_timeout(i915->gmbus_wait_queue, C,
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msecs_to_jiffies_timeout(timeout_ms));
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/* just trace the final value */
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trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
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if (!done)
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drm_err(&i915->drm,
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"%s: did not complete or timeout within %ums (status 0x%08x)\n",
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intel_dp->aux.name, timeout_ms, status);
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#undef C
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return status;
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}
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static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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if (index)
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return 0;
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/*
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* The clock divider is based off the hrawclk, and would like to run at
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* 2MHz. So, take the hrawclk value and divide by 2000 and use that
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*/
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return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
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}
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static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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u32 freq;
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if (index)
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return 0;
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/*
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* The clock divider is based off the cdclk or PCH rawclk, and would
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* like to run at 2MHz. So, take the cdclk or PCH rawclk value and
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* divide by 2000 and use that
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*/
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if (dig_port->aux_ch == AUX_CH_A)
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freq = dev_priv->cdclk.hw.cdclk;
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else
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freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
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return DIV_ROUND_CLOSEST(freq, 2000);
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}
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static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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{
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struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
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/* Workaround for non-ULT HSW */
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switch (index) {
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case 0: return 63;
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case 1: return 72;
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default: return 0;
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}
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}
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return ilk_get_aux_clock_divider(intel_dp, index);
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}
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static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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{
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/*
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* SKL doesn't need us to program the AUX clock divider (Hardware will
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* derive the clock from CDCLK automatically). We still implement the
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* get_aux_clock_divider vfunc to plug-in into the existing code.
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*/
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return index ? 0 : 1;
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}
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static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
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int send_bytes,
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u32 aux_clock_divider)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_i915_private *dev_priv =
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to_i915(dig_port->base.base.dev);
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u32 timeout;
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/* Max timeout value on G4x-BDW: 1.6ms */
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if (IS_BROADWELL(dev_priv))
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timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
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else
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timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
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return DP_AUX_CH_CTL_SEND_BUSY |
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DP_AUX_CH_CTL_DONE |
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DP_AUX_CH_CTL_INTERRUPT |
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DP_AUX_CH_CTL_TIME_OUT_ERROR |
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timeout |
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DP_AUX_CH_CTL_RECEIVE_ERROR |
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(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
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(3 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
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(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
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}
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static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
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int send_bytes,
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u32 unused)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_i915_private *i915 =
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to_i915(dig_port->base.base.dev);
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enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
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u32 ret;
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/*
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* Max timeout values:
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* SKL-GLK: 1.6ms
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* ICL+: 4ms
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*/
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ret = DP_AUX_CH_CTL_SEND_BUSY |
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DP_AUX_CH_CTL_DONE |
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DP_AUX_CH_CTL_INTERRUPT |
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DP_AUX_CH_CTL_TIME_OUT_ERROR |
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DP_AUX_CH_CTL_TIME_OUT_MAX |
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DP_AUX_CH_CTL_RECEIVE_ERROR |
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(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
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DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
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DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
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if (intel_phy_is_tc(i915, phy) &&
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dig_port->tc_mode == TC_PORT_TBT_ALT)
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ret |= DP_AUX_CH_CTL_TBT_IO;
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return ret;
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}
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static int
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intel_dp_aux_xfer(struct intel_dp *intel_dp,
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const u8 *send, int send_bytes,
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u8 *recv, int recv_size,
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u32 aux_send_ctl_flags)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_i915_private *i915 =
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to_i915(dig_port->base.base.dev);
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struct intel_uncore *uncore = &i915->uncore;
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enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
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bool is_tc_port = intel_phy_is_tc(i915, phy);
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i915_reg_t ch_ctl, ch_data[5];
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u32 aux_clock_divider;
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enum intel_display_power_domain aux_domain;
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intel_wakeref_t aux_wakeref;
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intel_wakeref_t pps_wakeref;
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int i, ret, recv_bytes;
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int try, clock = 0;
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u32 status;
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bool vdd;
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ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
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for (i = 0; i < ARRAY_SIZE(ch_data); i++)
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ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
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if (is_tc_port)
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intel_tc_port_lock(dig_port);
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aux_domain = intel_aux_power_domain(dig_port);
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aux_wakeref = intel_display_power_get(i915, aux_domain);
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pps_wakeref = intel_pps_lock(intel_dp);
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/*
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* We will be called with VDD already enabled for dpcd/edid/oui reads.
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* In such cases we want to leave VDD enabled and it's up to upper layers
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* to turn it off. But for eg. i2c-dev access we need to turn it on/off
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* ourselves.
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*/
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vdd = intel_pps_vdd_on_unlocked(intel_dp);
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/*
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* dp aux is extremely sensitive to irq latency, hence request the
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* lowest possible wakeup latency and so prevent the cpu from going into
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* deep sleep states.
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*/
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cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);
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intel_pps_check_power_unlocked(intel_dp);
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/* Try to wait for any previous AUX channel activity */
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for (try = 0; try < 3; try++) {
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status = intel_uncore_read_notrace(uncore, ch_ctl);
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if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
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break;
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msleep(1);
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}
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/* just trace the final value */
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trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
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if (try == 3) {
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const u32 status = intel_uncore_read(uncore, ch_ctl);
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if (status != intel_dp->aux_busy_last_status) {
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drm_WARN(&i915->drm, 1,
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"%s: not started (status 0x%08x)\n",
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intel_dp->aux.name, status);
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intel_dp->aux_busy_last_status = status;
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}
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ret = -EBUSY;
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goto out;
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}
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/* Only 5 data registers! */
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if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
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ret = -E2BIG;
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goto out;
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}
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while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
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u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
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send_bytes,
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aux_clock_divider);
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send_ctl |= aux_send_ctl_flags;
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/* Must try at least 3 times according to DP spec */
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for (try = 0; try < 5; try++) {
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/* Load the send data into the aux channel data registers */
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for (i = 0; i < send_bytes; i += 4)
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intel_uncore_write(uncore,
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ch_data[i >> 2],
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intel_dp_pack_aux(send + i,
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send_bytes - i));
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/* Send the command and wait for it to complete */
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intel_uncore_write(uncore, ch_ctl, send_ctl);
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status = intel_dp_aux_wait_done(intel_dp);
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/* Clear done status and any errors */
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intel_uncore_write(uncore,
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ch_ctl,
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status |
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DP_AUX_CH_CTL_DONE |
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DP_AUX_CH_CTL_TIME_OUT_ERROR |
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DP_AUX_CH_CTL_RECEIVE_ERROR);
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/*
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* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
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* 400us delay required for errors and timeouts
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* Timeout errors from the HW already meet this
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* requirement so skip to next iteration
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*/
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if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
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continue;
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if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
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usleep_range(400, 500);
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continue;
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}
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if (status & DP_AUX_CH_CTL_DONE)
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goto done;
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}
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}
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if ((status & DP_AUX_CH_CTL_DONE) == 0) {
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drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
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intel_dp->aux.name, status);
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ret = -EBUSY;
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goto out;
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}
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done:
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/*
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* Check for timeout or receive error. Timeouts occur when the sink is
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* not connected.
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*/
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if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
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drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
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intel_dp->aux.name, status);
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ret = -EIO;
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goto out;
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}
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/*
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* Timeouts occur when the device isn't connected, so they're "normal"
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* -- don't fill the kernel log with these
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*/
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if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
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drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
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intel_dp->aux.name, status);
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ret = -ETIMEDOUT;
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goto out;
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}
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/* Unload any bytes sent back from the other side */
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recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
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DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
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/*
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* By BSpec: "Message sizes of 0 or >20 are not allowed."
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* We have no idea of what happened so we return -EBUSY so
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* drm layer takes care for the necessary retries.
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*/
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if (recv_bytes == 0 || recv_bytes > 20) {
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drm_dbg_kms(&i915->drm,
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"%s: Forbidden recv_bytes = %d on aux transaction\n",
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intel_dp->aux.name, recv_bytes);
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ret = -EBUSY;
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goto out;
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}
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if (recv_bytes > recv_size)
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recv_bytes = recv_size;
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for (i = 0; i < recv_bytes; i += 4)
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intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
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recv + i, recv_bytes - i);
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ret = recv_bytes;
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out:
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cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
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if (vdd)
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intel_pps_vdd_off_unlocked(intel_dp, false);
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intel_pps_unlock(intel_dp, pps_wakeref);
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intel_display_power_put_async(i915, aux_domain, aux_wakeref);
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if (is_tc_port)
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intel_tc_port_unlock(dig_port);
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return ret;
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}
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#define BARE_ADDRESS_SIZE 3
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#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
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static void
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intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
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const struct drm_dp_aux_msg *msg)
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{
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txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
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txbuf[1] = (msg->address >> 8) & 0xff;
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txbuf[2] = msg->address & 0xff;
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txbuf[3] = msg->size - 1;
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}
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static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
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{
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/*
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* If we're trying to send the HDCP Aksv, we need to set a the Aksv
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* select bit to inform the hardware to send the Aksv after our header
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* since we can't access that data from software.
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*/
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if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
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msg->address == DP_AUX_HDCP_AKSV)
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return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
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return 0;
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}
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static ssize_t
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intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
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{
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struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
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struct drm_i915_private *i915 = dp_to_i915(intel_dp);
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u8 txbuf[20], rxbuf[20];
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size_t txsize, rxsize;
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u32 flags = intel_dp_aux_xfer_flags(msg);
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int ret;
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intel_dp_aux_header(txbuf, msg);
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switch (msg->request & ~DP_AUX_I2C_MOT) {
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case DP_AUX_NATIVE_WRITE:
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case DP_AUX_I2C_WRITE:
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case DP_AUX_I2C_WRITE_STATUS_UPDATE:
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txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
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rxsize = 2; /* 0 or 1 data bytes */
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if (drm_WARN_ON(&i915->drm, txsize > 20))
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return -E2BIG;
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drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
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if (msg->buffer)
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memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
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ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
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rxbuf, rxsize, flags);
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if (ret > 0) {
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msg->reply = rxbuf[0] >> 4;
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if (ret > 1) {
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/* Number of bytes written in a short write. */
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ret = clamp_t(int, rxbuf[1], 0, msg->size);
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} else {
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/* Return payload size. */
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ret = msg->size;
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}
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}
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break;
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case DP_AUX_NATIVE_READ:
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case DP_AUX_I2C_READ:
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txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
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rxsize = msg->size + 1;
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if (drm_WARN_ON(&i915->drm, rxsize > 20))
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return -E2BIG;
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ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
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rxbuf, rxsize, flags);
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if (ret > 0) {
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msg->reply = rxbuf[0] >> 4;
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/*
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* Assume happy day, and copy the data. The caller is
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* expected to check msg->reply before touching it.
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*
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* Return payload size.
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*/
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ret--;
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memcpy(msg->buffer, rxbuf + 1, ret);
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
|
|
|
|
static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
enum aux_ch aux_ch = dig_port->aux_ch;
|
|
|
|
switch (aux_ch) {
|
|
case AUX_CH_B:
|
|
case AUX_CH_C:
|
|
case AUX_CH_D:
|
|
return DP_AUX_CH_CTL(aux_ch);
|
|
default:
|
|
MISSING_CASE(aux_ch);
|
|
return DP_AUX_CH_CTL(AUX_CH_B);
|
|
}
|
|
}
|
|
|
|
static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
enum aux_ch aux_ch = dig_port->aux_ch;
|
|
|
|
switch (aux_ch) {
|
|
case AUX_CH_B:
|
|
case AUX_CH_C:
|
|
case AUX_CH_D:
|
|
return DP_AUX_CH_DATA(aux_ch, index);
|
|
default:
|
|
MISSING_CASE(aux_ch);
|
|
return DP_AUX_CH_DATA(AUX_CH_B, index);
|
|
}
|
|
}
|
|
|
|
static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
enum aux_ch aux_ch = dig_port->aux_ch;
|
|
|
|
switch (aux_ch) {
|
|
case AUX_CH_A:
|
|
return DP_AUX_CH_CTL(aux_ch);
|
|
case AUX_CH_B:
|
|
case AUX_CH_C:
|
|
case AUX_CH_D:
|
|
return PCH_DP_AUX_CH_CTL(aux_ch);
|
|
default:
|
|
MISSING_CASE(aux_ch);
|
|
return DP_AUX_CH_CTL(AUX_CH_A);
|
|
}
|
|
}
|
|
|
|
static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
enum aux_ch aux_ch = dig_port->aux_ch;
|
|
|
|
switch (aux_ch) {
|
|
case AUX_CH_A:
|
|
return DP_AUX_CH_DATA(aux_ch, index);
|
|
case AUX_CH_B:
|
|
case AUX_CH_C:
|
|
case AUX_CH_D:
|
|
return PCH_DP_AUX_CH_DATA(aux_ch, index);
|
|
default:
|
|
MISSING_CASE(aux_ch);
|
|
return DP_AUX_CH_DATA(AUX_CH_A, index);
|
|
}
|
|
}
|
|
|
|
static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
enum aux_ch aux_ch = dig_port->aux_ch;
|
|
|
|
switch (aux_ch) {
|
|
case AUX_CH_A:
|
|
case AUX_CH_B:
|
|
case AUX_CH_C:
|
|
case AUX_CH_D:
|
|
case AUX_CH_E:
|
|
case AUX_CH_F:
|
|
return DP_AUX_CH_CTL(aux_ch);
|
|
default:
|
|
MISSING_CASE(aux_ch);
|
|
return DP_AUX_CH_CTL(AUX_CH_A);
|
|
}
|
|
}
|
|
|
|
static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
enum aux_ch aux_ch = dig_port->aux_ch;
|
|
|
|
switch (aux_ch) {
|
|
case AUX_CH_A:
|
|
case AUX_CH_B:
|
|
case AUX_CH_C:
|
|
case AUX_CH_D:
|
|
case AUX_CH_E:
|
|
case AUX_CH_F:
|
|
return DP_AUX_CH_DATA(aux_ch, index);
|
|
default:
|
|
MISSING_CASE(aux_ch);
|
|
return DP_AUX_CH_DATA(AUX_CH_A, index);
|
|
}
|
|
}
|
|
|
|
static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
enum aux_ch aux_ch = dig_port->aux_ch;
|
|
|
|
switch (aux_ch) {
|
|
case AUX_CH_A:
|
|
case AUX_CH_B:
|
|
case AUX_CH_C:
|
|
case AUX_CH_USBC1:
|
|
case AUX_CH_USBC2:
|
|
case AUX_CH_USBC3:
|
|
case AUX_CH_USBC4:
|
|
case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
|
|
case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
|
|
return DP_AUX_CH_CTL(aux_ch);
|
|
default:
|
|
MISSING_CASE(aux_ch);
|
|
return DP_AUX_CH_CTL(AUX_CH_A);
|
|
}
|
|
}
|
|
|
|
static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
enum aux_ch aux_ch = dig_port->aux_ch;
|
|
|
|
switch (aux_ch) {
|
|
case AUX_CH_A:
|
|
case AUX_CH_B:
|
|
case AUX_CH_C:
|
|
case AUX_CH_USBC1:
|
|
case AUX_CH_USBC2:
|
|
case AUX_CH_USBC3:
|
|
case AUX_CH_USBC4:
|
|
case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
|
|
case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
|
|
return DP_AUX_CH_DATA(aux_ch, index);
|
|
default:
|
|
MISSING_CASE(aux_ch);
|
|
return DP_AUX_CH_DATA(AUX_CH_A, index);
|
|
}
|
|
}
|
|
|
|
void intel_dp_aux_fini(struct intel_dp *intel_dp)
|
|
{
|
|
if (cpu_latency_qos_request_active(&intel_dp->pm_qos))
|
|
cpu_latency_qos_remove_request(&intel_dp->pm_qos);
|
|
|
|
kfree(intel_dp->aux.name);
|
|
}
|
|
|
|
void intel_dp_aux_init(struct intel_dp *intel_dp)
|
|
{
|
|
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
struct intel_encoder *encoder = &dig_port->base;
|
|
enum aux_ch aux_ch = dig_port->aux_ch;
|
|
|
|
if (DISPLAY_VER(dev_priv) >= 12) {
|
|
intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
|
|
intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
|
|
} else if (DISPLAY_VER(dev_priv) >= 9) {
|
|
intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
|
|
intel_dp->aux_ch_data_reg = skl_aux_data_reg;
|
|
} else if (HAS_PCH_SPLIT(dev_priv)) {
|
|
intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
|
|
intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
|
|
} else {
|
|
intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
|
|
intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
|
|
}
|
|
|
|
if (DISPLAY_VER(dev_priv) >= 9)
|
|
intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
|
|
else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
|
|
intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
|
|
else if (HAS_PCH_SPLIT(dev_priv))
|
|
intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
|
|
else
|
|
intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
|
|
|
|
if (DISPLAY_VER(dev_priv) >= 9)
|
|
intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
|
|
else
|
|
intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
|
|
|
|
intel_dp->aux.drm_dev = &dev_priv->drm;
|
|
drm_dp_aux_init(&intel_dp->aux);
|
|
|
|
/* Failure to allocate our preferred name is not critical */
|
|
if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD)
|
|
intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
|
|
aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D),
|
|
encoder->base.name);
|
|
else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
|
|
intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
|
|
aux_ch - AUX_CH_USBC1 + '1',
|
|
encoder->base.name);
|
|
else
|
|
intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
|
|
aux_ch_name(aux_ch),
|
|
encoder->base.name);
|
|
|
|
intel_dp->aux.transfer = intel_dp_aux_transfer;
|
|
cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);
|
|
}
|