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afeda4f3b1
Pre-allocate command buffer in atomic_commit using intel_dsb_prepare function which also includes pinning and map in cpu domain. No functional change is dsb write/commit functions. Now dsb get/put function is removed and ref-count mechanism is not needed. Below dsb api added to do respective job mentioned below. intel_dsb_prepare - Allocate, pin and map the buffer. intel_dsb_cleanup - Unpin and release the gem object. RFC: Initial patch for design review. v2: included _init() part in _prepare(). [Daniel, Ville] v3: dsb_cleanup called after cleanup_planes. [Daniel] v4: dsb structure is moved to intel_crtc_state from intel_crtc. [Maarten] v5: dsb get/put/ref-count mechanism removed. [Maarten] v6: Based on review feedback following changes are added, - replaced intel_dsb structure by pointer in intel_crtc_state. [Maarten] - passing intel_crtc_state to dsp-api to simplify the code. [Maarten] - few dsb functions prototype modified to simplify code. v7: added few cosmetic changes suggested by Jani and null check for crtc_state in dsb_cleanup removed as suggested by Maarten. v8: changed the function parameter to intel_crtc_state* of ivb_load_lut_ext_max() from intel_crtc. [Maarten] v9: error handling improved in _write() and prepare(). [Maarten] Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200520130737.11240-1-animesh.manna@intel.com
51 lines
1.1 KiB
C
51 lines
1.1 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef _INTEL_DSB_H
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#define _INTEL_DSB_H
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#include <linux/types.h>
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#include "i915_reg.h"
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struct intel_crtc_state;
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struct i915_vma;
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enum dsb_id {
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INVALID_DSB = -1,
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DSB1,
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DSB2,
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DSB3,
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MAX_DSB_PER_PIPE
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};
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struct intel_dsb {
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enum dsb_id id;
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u32 *cmd_buf;
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struct i915_vma *vma;
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/*
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* free_pos will point the first free entry position
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* and help in calculating tail of command buffer.
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*/
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int free_pos;
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/*
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* ins_start_offset will help to store start address of the dsb
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* instuction and help in identifying the batch of auto-increment
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* register.
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*/
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u32 ins_start_offset;
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};
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void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
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void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
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void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state,
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i915_reg_t reg, u32 val);
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void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state,
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i915_reg_t reg, u32 val);
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void intel_dsb_commit(const struct intel_crtc_state *crtc_state);
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#endif
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