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3b4da8315a
We use encoder->get_buf_trans() in many places, for example intel_ddi_dp_voltage_max(), and the hook was set to some old platform's function for DG2 SNPS PHY. Convert SNPS PHY to use the same translation mechanisms as everything else. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210813115151.19290-2-jani.nikula@intel.com
36 lines
1.1 KiB
C
36 lines
1.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_SNPS_PHY_H__
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#define __INTEL_SNPS_PHY_H__
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#include <linux/types.h>
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struct drm_i915_private;
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struct intel_encoder;
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struct intel_crtc_state;
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struct intel_mpllb_state;
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enum phy;
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void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv);
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void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
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enum phy phy, bool enable);
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int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
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struct intel_encoder *encoder);
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void intel_mpllb_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state);
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void intel_mpllb_disable(struct intel_encoder *encoder);
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void intel_mpllb_readout_hw_state(struct intel_encoder *encoder,
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struct intel_mpllb_state *pll_state);
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int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
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const struct intel_mpllb_state *pll_state);
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int intel_snps_phy_check_hdmi_link_rate(int clock);
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void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state,
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int level);
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#endif /* __INTEL_SNPS_PHY_H__ */
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