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![Lucas De Marchi](/assets/img/avatar_default.png)
With the removal of CNL, let's consider GLK as the first platform using those constants since GLK has DISPLAY_VER == 10. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210728215946.1573015-16-lucas.demarchi@intel.com
556 lines
18 KiB
C
556 lines
18 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2020 Intel Corporation
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*/
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "skl_scaler.h"
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#include "skl_universal_plane.h"
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/*
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* The hardware phase 0.0 refers to the center of the pixel.
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* We want to start from the top/left edge which is phase
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* -0.5. That matches how the hardware calculates the scaling
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* factors (from top-left of the first pixel to bottom-right
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* of the last pixel, as opposed to the pixel centers).
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*
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* For 4:2:0 subsampled chroma planes we obviously have to
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* adjust that so that the chroma sample position lands in
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* the right spot.
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*
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* Note that for packed YCbCr 4:2:2 formats there is no way to
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* control chroma siting. The hardware simply replicates the
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* chroma samples for both of the luma samples, and thus we don't
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* actually get the expected MPEG2 chroma siting convention :(
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* The same behaviour is observed on pre-SKL platforms as well.
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*
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* Theory behind the formula (note that we ignore sub-pixel
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* source coordinates):
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* s = source sample position
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* d = destination sample position
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*
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* Downscaling 4:1:
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* -0.5
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* | 0.0
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* | | 1.5 (initial phase)
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* | | |
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* v v v
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* | s | s | s | s |
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* | d |
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*
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* Upscaling 1:4:
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* -0.5
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* | -0.375 (initial phase)
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* | | 0.0
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* | | |
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* v v v
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* | s |
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* | d | d | d | d |
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*/
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static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
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{
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int phase = -0x8000;
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u16 trip = 0;
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if (chroma_cosited)
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phase += (sub - 1) * 0x8000 / sub;
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phase += scale / (2 * sub);
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/*
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* Hardware initial phase limited to [-0.5:1.5].
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* Since the max hardware scale factor is 3.0, we
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* should never actually excdeed 1.0 here.
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*/
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WARN_ON(phase < -0x8000 || phase > 0x18000);
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if (phase < 0)
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phase = 0x10000 + phase;
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else
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trip = PS_PHASE_TRIP;
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return ((phase >> 2) & PS_PHASE_MASK) | trip;
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}
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#define SKL_MIN_SRC_W 8
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#define SKL_MAX_SRC_W 4096
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#define SKL_MIN_SRC_H 8
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#define SKL_MAX_SRC_H 4096
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#define SKL_MIN_DST_W 8
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#define SKL_MAX_DST_W 4096
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#define SKL_MIN_DST_H 8
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#define SKL_MAX_DST_H 4096
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#define ICL_MAX_SRC_W 5120
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#define ICL_MAX_SRC_H 4096
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#define ICL_MAX_DST_W 5120
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#define ICL_MAX_DST_H 4096
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#define SKL_MIN_YUV_420_SRC_W 16
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#define SKL_MIN_YUV_420_SRC_H 16
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static int
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skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
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unsigned int scaler_user, int *scaler_id,
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int src_w, int src_h, int dst_w, int dst_h,
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const struct drm_format_info *format,
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u64 modifier, bool need_scaler)
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{
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struct intel_crtc_scaler_state *scaler_state =
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&crtc_state->scaler_state;
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct drm_display_mode *adjusted_mode =
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&crtc_state->hw.adjusted_mode;
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/*
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* Src coordinates are already rotated by 270 degrees for
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* the 90/270 degree plane rotation cases (to match the
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* GTT mapping), hence no need to account for rotation here.
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*/
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if (src_w != dst_w || src_h != dst_h)
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need_scaler = true;
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/*
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* Scaling/fitting not supported in IF-ID mode in GEN9+
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* TODO: Interlace fetch mode doesn't support YUV420 planar formats.
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* Once NV12 is enabled, handle it here while allocating scaler
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* for NV12.
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*/
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if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable &&
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need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
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drm_dbg_kms(&dev_priv->drm,
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"Pipe/Plane scaling not supported with IF-ID mode\n");
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return -EINVAL;
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}
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/*
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* if plane is being disabled or scaler is no more required or force detach
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* - free scaler binded to this plane/crtc
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* - in order to do this, update crtc->scaler_usage
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*
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* Here scaler state in crtc_state is set free so that
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* scaler can be assigned to other user. Actual register
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* update to free the scaler is done in plane/panel-fit programming.
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* For this purpose crtc/plane_state->scaler_id isn't reset here.
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*/
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if (force_detach || !need_scaler) {
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if (*scaler_id >= 0) {
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scaler_state->scaler_users &= ~(1 << scaler_user);
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scaler_state->scalers[*scaler_id].in_use = 0;
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drm_dbg_kms(&dev_priv->drm,
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"scaler_user index %u.%u: "
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"Staged freeing scaler id %d scaler_users = 0x%x\n",
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crtc->pipe, scaler_user, *scaler_id,
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scaler_state->scaler_users);
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*scaler_id = -1;
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}
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return 0;
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}
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if (format && intel_format_info_is_yuv_semiplanar(format, modifier) &&
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(src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
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drm_dbg_kms(&dev_priv->drm,
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"Planar YUV: src dimensions not met\n");
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return -EINVAL;
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}
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/* range checks */
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if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
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dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
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(DISPLAY_VER(dev_priv) >= 11 &&
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(src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
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dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
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(DISPLAY_VER(dev_priv) < 11 &&
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(src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
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dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) {
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drm_dbg_kms(&dev_priv->drm,
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"scaler_user index %u.%u: src %ux%u dst %ux%u "
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"size is out of scaler range\n",
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crtc->pipe, scaler_user, src_w, src_h,
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dst_w, dst_h);
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return -EINVAL;
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}
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/* mark this plane as a scaler user in crtc_state */
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scaler_state->scaler_users |= (1 << scaler_user);
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drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "
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"staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
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crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
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scaler_state->scaler_users);
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return 0;
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}
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int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
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{
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const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
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int width, height;
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if (crtc_state->pch_pfit.enabled) {
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width = drm_rect_width(&crtc_state->pch_pfit.dst);
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height = drm_rect_height(&crtc_state->pch_pfit.dst);
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} else {
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width = pipe_mode->crtc_hdisplay;
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height = pipe_mode->crtc_vdisplay;
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}
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return skl_update_scaler(crtc_state, !crtc_state->hw.active,
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SKL_CRTC_INDEX,
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&crtc_state->scaler_state.scaler_id,
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crtc_state->pipe_src_w, crtc_state->pipe_src_h,
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width, height, NULL, 0,
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crtc_state->pch_pfit.enabled);
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}
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/**
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* skl_update_scaler_plane - Stages update to scaler state for a given plane.
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* @crtc_state: crtc's scaler state
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* @plane_state: atomic plane state to update
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*
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* Return
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* 0 - scaler_usage updated successfully
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* error - requested scaling cannot be supported or other error condition
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*/
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int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
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struct intel_plane_state *plane_state)
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{
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struct intel_plane *intel_plane =
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to_intel_plane(plane_state->uapi.plane);
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struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
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struct drm_framebuffer *fb = plane_state->hw.fb;
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int ret;
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bool force_detach = !fb || !plane_state->uapi.visible;
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bool need_scaler = false;
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/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
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if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
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fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
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need_scaler = true;
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ret = skl_update_scaler(crtc_state, force_detach,
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drm_plane_index(&intel_plane->base),
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&plane_state->scaler_id,
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drm_rect_width(&plane_state->uapi.src) >> 16,
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drm_rect_height(&plane_state->uapi.src) >> 16,
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drm_rect_width(&plane_state->uapi.dst),
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drm_rect_height(&plane_state->uapi.dst),
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fb ? fb->format : NULL,
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fb ? fb->modifier : 0,
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need_scaler);
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if (ret || plane_state->scaler_id < 0)
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return ret;
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/* check colorkey */
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if (plane_state->ckey.flags) {
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drm_dbg_kms(&dev_priv->drm,
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"[PLANE:%d:%s] scaling with color key not allowed",
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intel_plane->base.base.id,
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intel_plane->base.name);
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return -EINVAL;
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}
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/* Check src format */
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switch (fb->format->format) {
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case DRM_FORMAT_RGB565:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_XRGB2101010:
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case DRM_FORMAT_XBGR2101010:
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case DRM_FORMAT_ARGB2101010:
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case DRM_FORMAT_ABGR2101010:
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case DRM_FORMAT_YUYV:
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case DRM_FORMAT_YVYU:
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case DRM_FORMAT_UYVY:
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case DRM_FORMAT_VYUY:
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case DRM_FORMAT_NV12:
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case DRM_FORMAT_XYUV8888:
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case DRM_FORMAT_P010:
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case DRM_FORMAT_P012:
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case DRM_FORMAT_P016:
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case DRM_FORMAT_Y210:
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case DRM_FORMAT_Y212:
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case DRM_FORMAT_Y216:
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case DRM_FORMAT_XVYU2101010:
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case DRM_FORMAT_XVYU12_16161616:
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case DRM_FORMAT_XVYU16161616:
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break;
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case DRM_FORMAT_XBGR16161616F:
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case DRM_FORMAT_ABGR16161616F:
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case DRM_FORMAT_XRGB16161616F:
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case DRM_FORMAT_ARGB16161616F:
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if (DISPLAY_VER(dev_priv) >= 11)
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break;
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fallthrough;
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default:
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drm_dbg_kms(&dev_priv->drm,
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"[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
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intel_plane->base.base.id, intel_plane->base.name,
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fb->base.id, fb->format->format);
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return -EINVAL;
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}
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return 0;
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}
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static int glk_coef_tap(int i)
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{
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return i % 7;
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}
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static u16 glk_nearest_filter_coef(int t)
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{
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return t == 3 ? 0x0800 : 0x3000;
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}
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/*
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* Theory behind setting nearest-neighbor integer scaling:
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*
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* 17 phase of 7 taps requires 119 coefficients in 60 dwords per set.
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* The letter represents the filter tap (D is the center tap) and the number
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* represents the coefficient set for a phase (0-16).
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*
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* +------------+------------------------+------------------------+
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* |Index value | Data value coeffient 1 | Data value coeffient 2 |
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* +------------+------------------------+------------------------+
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* | 00h | B0 | A0 |
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* +------------+------------------------+------------------------+
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* | 01h | D0 | C0 |
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* +------------+------------------------+------------------------+
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* | 02h | F0 | E0 |
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* +------------+------------------------+------------------------+
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* | 03h | A1 | G0 |
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* +------------+------------------------+------------------------+
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* | 04h | C1 | B1 |
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* +------------+------------------------+------------------------+
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* | ... | ... | ... |
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* +------------+------------------------+------------------------+
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* | 38h | B16 | A16 |
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* +------------+------------------------+------------------------+
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* | 39h | D16 | C16 |
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* +------------+------------------------+------------------------+
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* | 3Ah | F16 | C16 |
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* +------------+------------------------+------------------------+
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* | 3Bh | Reserved | G16 |
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* +------------+------------------------+------------------------+
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*
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* To enable nearest-neighbor scaling: program scaler coefficents with
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* the center tap (Dxx) values set to 1 and all other values set to 0 as per
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* SCALER_COEFFICIENT_FORMAT
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*
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*/
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static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv,
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enum pipe pipe, int id, int set)
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{
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int i;
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intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set),
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PS_COEE_INDEX_AUTO_INC);
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for (i = 0; i < 17 * 7; i += 2) {
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u32 tmp;
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int t;
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t = glk_coef_tap(i);
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tmp = glk_nearest_filter_coef(t);
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t = glk_coef_tap(i + 1);
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tmp |= glk_nearest_filter_coef(t) << 16;
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intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set),
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tmp);
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}
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intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0);
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}
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static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set)
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{
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if (filter == DRM_SCALING_FILTER_NEAREST_NEIGHBOR) {
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return (PS_FILTER_PROGRAMMED |
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PS_Y_VERT_FILTER_SELECT(set) |
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PS_Y_HORZ_FILTER_SELECT(set) |
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PS_UV_VERT_FILTER_SELECT(set) |
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PS_UV_HORZ_FILTER_SELECT(set));
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}
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return PS_FILTER_MEDIUM;
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}
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static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe,
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int id, int set, enum drm_scaling_filter filter)
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{
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switch (filter) {
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case DRM_SCALING_FILTER_DEFAULT:
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break;
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case DRM_SCALING_FILTER_NEAREST_NEIGHBOR:
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glk_program_nearest_filter_coefs(dev_priv, pipe, id, set);
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break;
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default:
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MISSING_CASE(filter);
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}
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}
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void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
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{
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struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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const struct intel_crtc_scaler_state *scaler_state =
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&crtc_state->scaler_state;
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struct drm_rect src = {
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.x2 = crtc_state->pipe_src_w << 16,
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.y2 = crtc_state->pipe_src_h << 16,
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};
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const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
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u16 uv_rgb_hphase, uv_rgb_vphase;
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enum pipe pipe = crtc->pipe;
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int width = drm_rect_width(dst);
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int height = drm_rect_height(dst);
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int x = dst->x1;
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int y = dst->y1;
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int hscale, vscale;
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unsigned long irqflags;
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int id;
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u32 ps_ctrl;
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if (!crtc_state->pch_pfit.enabled)
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return;
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if (drm_WARN_ON(&dev_priv->drm,
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crtc_state->scaler_state.scaler_id < 0))
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return;
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hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
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vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
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uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
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uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
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id = scaler_state->scaler_id;
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ps_ctrl = skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0);
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ps_ctrl |= PS_SCALER_EN | scaler_state->scalers[id].mode;
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spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
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skl_scaler_setup_filter(dev_priv, pipe, id, 0,
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crtc_state->hw.scaling_filter);
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intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl);
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intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id),
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PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
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intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id),
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PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
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intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id),
|
|
x << 16 | y);
|
|
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id),
|
|
width << 16 | height);
|
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
|
}
|
|
|
|
void
|
|
skl_program_plane_scaler(struct intel_plane *plane,
|
|
const struct intel_crtc_state *crtc_state,
|
|
const struct intel_plane_state *plane_state)
|
|
{
|
|
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
|
|
const struct drm_framebuffer *fb = plane_state->hw.fb;
|
|
enum pipe pipe = plane->pipe;
|
|
int scaler_id = plane_state->scaler_id;
|
|
const struct intel_scaler *scaler =
|
|
&crtc_state->scaler_state.scalers[scaler_id];
|
|
int crtc_x = plane_state->uapi.dst.x1;
|
|
int crtc_y = plane_state->uapi.dst.y1;
|
|
u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
|
|
u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
|
|
u16 y_hphase, uv_rgb_hphase;
|
|
u16 y_vphase, uv_rgb_vphase;
|
|
int hscale, vscale;
|
|
u32 ps_ctrl;
|
|
|
|
hscale = drm_rect_calc_hscale(&plane_state->uapi.src,
|
|
&plane_state->uapi.dst,
|
|
0, INT_MAX);
|
|
vscale = drm_rect_calc_vscale(&plane_state->uapi.src,
|
|
&plane_state->uapi.dst,
|
|
0, INT_MAX);
|
|
|
|
/* TODO: handle sub-pixel coordinates */
|
|
if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
|
|
!icl_is_hdr_plane(dev_priv, plane->id)) {
|
|
y_hphase = skl_scaler_calc_phase(1, hscale, false);
|
|
y_vphase = skl_scaler_calc_phase(1, vscale, false);
|
|
|
|
/* MPEG2 chroma siting convention */
|
|
uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true);
|
|
uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false);
|
|
} else {
|
|
/* not used */
|
|
y_hphase = 0;
|
|
y_vphase = 0;
|
|
|
|
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
|
|
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
|
|
}
|
|
|
|
ps_ctrl = skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0);
|
|
ps_ctrl |= PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode;
|
|
|
|
skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0,
|
|
plane_state->hw.scaling_filter);
|
|
|
|
intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
|
|
intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id),
|
|
PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase));
|
|
intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id),
|
|
PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase));
|
|
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id),
|
|
(crtc_x << 16) | crtc_y);
|
|
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id),
|
|
(crtc_w << 16) | crtc_h);
|
|
}
|
|
|
|
static void skl_detach_scaler(struct intel_crtc *crtc, int id)
|
|
{
|
|
struct drm_device *dev = crtc->base.dev;
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
unsigned long irqflags;
|
|
|
|
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
|
|
|
|
intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0);
|
|
intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0);
|
|
intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0);
|
|
|
|
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
|
|
}
|
|
|
|
/*
|
|
* This function detaches (aka. unbinds) unused scalers in hardware
|
|
*/
|
|
void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
|
|
{
|
|
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
|
const struct intel_crtc_scaler_state *scaler_state =
|
|
&crtc_state->scaler_state;
|
|
int i;
|
|
|
|
/* loop through and disable scalers that aren't in use */
|
|
for (i = 0; i < crtc->num_scalers; i++) {
|
|
if (!scaler_state->scalers[i].in_use)
|
|
skl_detach_scaler(crtc, i);
|
|
}
|
|
}
|
|
|
|
void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
|
|
{
|
|
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
|
|
int i;
|
|
|
|
for (i = 0; i < crtc->num_scalers; i++)
|
|
skl_detach_scaler(crtc, i);
|
|
}
|