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![Lucas De Marchi](/assets/img/avatar_default.png)
Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with {==,>=} 11. With the removal of CNL, there is no platform with graphics version equals 10. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210728215946.1573015-24-lucas.demarchi@intel.com
1030 lines
30 KiB
C
1030 lines
30 KiB
C
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Keith Packard <keithp@keithp.com>
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*
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*/
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#include <linux/sched/mm.h>
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#include <linux/sort.h>
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#include <drm/drm_debugfs.h>
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#include "gem/i915_gem_context.h"
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#include "gt/intel_gt_buffer_pool.h"
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#include "gt/intel_gt_clock_utils.h"
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#include "gt/intel_gt.h"
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#include "gt/intel_gt_pm.h"
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#include "gt/intel_gt_requests.h"
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#include "gt/intel_reset.h"
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#include "gt/intel_rc6.h"
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#include "gt/intel_rps.h"
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#include "gt/intel_sseu_debugfs.h"
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#include "i915_debugfs.h"
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#include "i915_debugfs_params.h"
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#include "i915_irq.h"
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#include "i915_scheduler.h"
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#include "i915_trace.h"
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#include "intel_pm.h"
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#include "intel_sideband.h"
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static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
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{
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return to_i915(node->minor->dev);
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}
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static int i915_capabilities(struct seq_file *m, void *data)
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{
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struct drm_i915_private *i915 = node_to_i915(m->private);
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struct drm_printer p = drm_seq_file_printer(m);
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seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
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intel_device_info_print_static(INTEL_INFO(i915), &p);
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intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
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intel_gt_info_print(&i915->gt.info, &p);
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intel_driver_caps_print(&i915->caps, &p);
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kernel_param_lock(THIS_MODULE);
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i915_params_dump(&i915->params, &p);
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kernel_param_unlock(THIS_MODULE);
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return 0;
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}
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static char get_tiling_flag(struct drm_i915_gem_object *obj)
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{
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switch (i915_gem_object_get_tiling(obj)) {
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default:
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case I915_TILING_NONE: return ' ';
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case I915_TILING_X: return 'X';
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case I915_TILING_Y: return 'Y';
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}
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}
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static char get_global_flag(struct drm_i915_gem_object *obj)
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{
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return READ_ONCE(obj->userfault_count) ? 'g' : ' ';
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}
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static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
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{
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return obj->mm.mapping ? 'M' : ' ';
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}
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static const char *
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stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
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{
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size_t x = 0;
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switch (page_sizes) {
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case 0:
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return "";
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case I915_GTT_PAGE_SIZE_4K:
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return "4K";
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case I915_GTT_PAGE_SIZE_64K:
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return "64K";
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case I915_GTT_PAGE_SIZE_2M:
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return "2M";
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default:
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if (!buf)
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return "M";
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if (page_sizes & I915_GTT_PAGE_SIZE_2M)
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x += snprintf(buf + x, len - x, "2M, ");
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if (page_sizes & I915_GTT_PAGE_SIZE_64K)
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x += snprintf(buf + x, len - x, "64K, ");
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if (page_sizes & I915_GTT_PAGE_SIZE_4K)
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x += snprintf(buf + x, len - x, "4K, ");
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buf[x-2] = '\0';
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return buf;
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}
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}
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static const char *stringify_vma_type(const struct i915_vma *vma)
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{
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if (i915_vma_is_ggtt(vma))
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return "ggtt";
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if (i915_vma_is_dpt(vma))
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return "dpt";
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return "ppgtt";
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}
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void
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i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
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{
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struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
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struct intel_engine_cs *engine;
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struct i915_vma *vma;
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int pin_count = 0;
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seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s",
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&obj->base,
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get_tiling_flag(obj),
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get_global_flag(obj),
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get_pin_mapped_flag(obj),
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obj->base.size / 1024,
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obj->read_domains,
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obj->write_domain,
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i915_cache_level_str(dev_priv, obj->cache_level),
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obj->mm.dirty ? " dirty" : "",
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obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
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if (obj->base.name)
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seq_printf(m, " (name: %d)", obj->base.name);
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spin_lock(&obj->vma.lock);
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list_for_each_entry(vma, &obj->vma.list, obj_link) {
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if (!drm_mm_node_allocated(&vma->node))
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continue;
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spin_unlock(&obj->vma.lock);
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if (i915_vma_is_pinned(vma))
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pin_count++;
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seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
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stringify_vma_type(vma),
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vma->node.start, vma->node.size,
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stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
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if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
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switch (vma->ggtt_view.type) {
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case I915_GGTT_VIEW_NORMAL:
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seq_puts(m, ", normal");
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break;
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case I915_GGTT_VIEW_PARTIAL:
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seq_printf(m, ", partial [%08llx+%x]",
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vma->ggtt_view.partial.offset << PAGE_SHIFT,
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vma->ggtt_view.partial.size << PAGE_SHIFT);
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break;
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case I915_GGTT_VIEW_ROTATED:
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seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
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vma->ggtt_view.rotated.plane[0].width,
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vma->ggtt_view.rotated.plane[0].height,
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vma->ggtt_view.rotated.plane[0].src_stride,
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vma->ggtt_view.rotated.plane[0].dst_stride,
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vma->ggtt_view.rotated.plane[0].offset,
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vma->ggtt_view.rotated.plane[1].width,
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vma->ggtt_view.rotated.plane[1].height,
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vma->ggtt_view.rotated.plane[1].src_stride,
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vma->ggtt_view.rotated.plane[1].dst_stride,
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vma->ggtt_view.rotated.plane[1].offset);
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break;
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case I915_GGTT_VIEW_REMAPPED:
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seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
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vma->ggtt_view.remapped.plane[0].width,
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vma->ggtt_view.remapped.plane[0].height,
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vma->ggtt_view.remapped.plane[0].src_stride,
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vma->ggtt_view.remapped.plane[0].dst_stride,
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vma->ggtt_view.remapped.plane[0].offset,
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vma->ggtt_view.remapped.plane[1].width,
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vma->ggtt_view.remapped.plane[1].height,
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vma->ggtt_view.remapped.plane[1].src_stride,
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vma->ggtt_view.remapped.plane[1].dst_stride,
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vma->ggtt_view.remapped.plane[1].offset);
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break;
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default:
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MISSING_CASE(vma->ggtt_view.type);
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break;
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}
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}
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if (vma->fence)
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seq_printf(m, " , fence: %d", vma->fence->id);
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seq_puts(m, ")");
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spin_lock(&obj->vma.lock);
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}
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spin_unlock(&obj->vma.lock);
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seq_printf(m, " (pinned x %d)", pin_count);
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if (i915_gem_object_is_stolen(obj))
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seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
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if (i915_gem_object_is_framebuffer(obj))
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seq_printf(m, " (fb)");
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engine = i915_gem_object_last_write_engine(obj);
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if (engine)
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seq_printf(m, " (%s)", engine->name);
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}
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static int i915_gem_object_info(struct seq_file *m, void *data)
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{
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struct drm_i915_private *i915 = node_to_i915(m->private);
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struct intel_memory_region *mr;
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enum intel_region_id id;
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seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n",
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i915->mm.shrink_count,
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atomic_read(&i915->mm.free_count),
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i915->mm.shrink_memory);
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for_each_memory_region(mr, i915, id)
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seq_printf(m, "%s: total:%pa, available:%pa bytes\n",
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mr->name, &mr->total, &mr->avail);
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return 0;
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}
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#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
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static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
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size_t count, loff_t *pos)
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{
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struct i915_gpu_coredump *error;
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ssize_t ret;
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void *buf;
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error = file->private_data;
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if (!error)
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return 0;
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/* Bounce buffer required because of kernfs __user API convenience. */
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buf = kmalloc(count, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count);
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if (ret <= 0)
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goto out;
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if (!copy_to_user(ubuf, buf, ret))
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*pos += ret;
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else
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ret = -EFAULT;
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out:
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kfree(buf);
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return ret;
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}
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static int gpu_state_release(struct inode *inode, struct file *file)
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{
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i915_gpu_coredump_put(file->private_data);
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return 0;
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}
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static int i915_gpu_info_open(struct inode *inode, struct file *file)
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{
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struct drm_i915_private *i915 = inode->i_private;
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struct i915_gpu_coredump *gpu;
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intel_wakeref_t wakeref;
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gpu = NULL;
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with_intel_runtime_pm(&i915->runtime_pm, wakeref)
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gpu = i915_gpu_coredump(&i915->gt, ALL_ENGINES);
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if (IS_ERR(gpu))
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return PTR_ERR(gpu);
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file->private_data = gpu;
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return 0;
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}
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static const struct file_operations i915_gpu_info_fops = {
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.owner = THIS_MODULE,
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.open = i915_gpu_info_open,
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.read = gpu_state_read,
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.llseek = default_llseek,
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.release = gpu_state_release,
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};
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static ssize_t
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i915_error_state_write(struct file *filp,
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const char __user *ubuf,
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size_t cnt,
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loff_t *ppos)
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{
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struct i915_gpu_coredump *error = filp->private_data;
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if (!error)
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return 0;
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drm_dbg(&error->i915->drm, "Resetting error state\n");
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i915_reset_error_state(error->i915);
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return cnt;
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}
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static int i915_error_state_open(struct inode *inode, struct file *file)
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{
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struct i915_gpu_coredump *error;
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error = i915_first_error_state(inode->i_private);
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if (IS_ERR(error))
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return PTR_ERR(error);
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file->private_data = error;
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return 0;
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}
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static const struct file_operations i915_error_state_fops = {
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.owner = THIS_MODULE,
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.open = i915_error_state_open,
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.read = gpu_state_read,
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.write = i915_error_state_write,
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.llseek = default_llseek,
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.release = gpu_state_release,
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};
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#endif
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static int i915_frequency_info(struct seq_file *m, void *unused)
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{
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struct drm_i915_private *dev_priv = node_to_i915(m->private);
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struct intel_uncore *uncore = &dev_priv->uncore;
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struct intel_rps *rps = &dev_priv->gt.rps;
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intel_wakeref_t wakeref;
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wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
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if (GRAPHICS_VER(dev_priv) == 5) {
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u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
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u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
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seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
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seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
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seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
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MEMSTAT_VID_SHIFT);
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seq_printf(m, "Current P-state: %d\n",
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(rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
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} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
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u32 rpmodectl, freq_sts;
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rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL);
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seq_printf(m, "Video Turbo Mode: %s\n",
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yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
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seq_printf(m, "HW control enabled: %s\n",
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yesno(rpmodectl & GEN6_RP_ENABLE));
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seq_printf(m, "SW control enabled: %s\n",
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yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
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GEN6_RP_MEDIA_SW_MODE));
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vlv_punit_get(dev_priv);
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freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
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vlv_punit_put(dev_priv);
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seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
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seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
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seq_printf(m, "actual GPU freq: %d MHz\n",
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intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
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seq_printf(m, "current GPU freq: %d MHz\n",
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intel_gpu_freq(rps, rps->cur_freq));
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seq_printf(m, "max GPU freq: %d MHz\n",
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intel_gpu_freq(rps, rps->max_freq));
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seq_printf(m, "min GPU freq: %d MHz\n",
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intel_gpu_freq(rps, rps->min_freq));
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seq_printf(m, "idle GPU freq: %d MHz\n",
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intel_gpu_freq(rps, rps->idle_freq));
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seq_printf(m,
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"efficient (RPe) frequency: %d MHz\n",
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intel_gpu_freq(rps, rps->efficient_freq));
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} else if (GRAPHICS_VER(dev_priv) >= 6) {
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u32 rp_state_limits;
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u32 gt_perf_status;
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u32 rp_state_cap;
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u32 rpmodectl, rpinclimit, rpdeclimit;
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u32 rpstat, cagf, reqf;
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u32 rpupei, rpcurup, rpprevup;
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u32 rpdownei, rpcurdown, rpprevdown;
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u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
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int max_freq;
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rp_state_limits = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_LIMITS);
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if (IS_GEN9_LP(dev_priv)) {
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rp_state_cap = intel_uncore_read(&dev_priv->uncore, BXT_RP_STATE_CAP);
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gt_perf_status = intel_uncore_read(&dev_priv->uncore, BXT_GT_PERF_STATUS);
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} else {
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rp_state_cap = intel_uncore_read(&dev_priv->uncore, GEN6_RP_STATE_CAP);
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gt_perf_status = intel_uncore_read(&dev_priv->uncore, GEN6_GT_PERF_STATUS);
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}
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/* RPSTAT1 is in the GT power well */
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intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
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reqf = intel_uncore_read(&dev_priv->uncore, GEN6_RPNSWREQ);
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if (GRAPHICS_VER(dev_priv) >= 9)
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reqf >>= 23;
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else {
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reqf &= ~GEN6_TURBO_DISABLE;
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
|
|
reqf >>= 24;
|
|
else
|
|
reqf >>= 25;
|
|
}
|
|
reqf = intel_gpu_freq(rps, reqf);
|
|
|
|
rpmodectl = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CONTROL);
|
|
rpinclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_UP_THRESHOLD);
|
|
rpdeclimit = intel_uncore_read(&dev_priv->uncore, GEN6_RP_DOWN_THRESHOLD);
|
|
|
|
rpstat = intel_uncore_read(&dev_priv->uncore, GEN6_RPSTAT1);
|
|
rpupei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
|
|
rpcurup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
|
|
rpprevup = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
|
|
rpdownei = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
|
|
rpcurdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
|
|
rpprevdown = intel_uncore_read(&dev_priv->uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
|
|
cagf = intel_rps_read_actual_frequency(rps);
|
|
|
|
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
|
|
|
|
if (GRAPHICS_VER(dev_priv) >= 11) {
|
|
pm_ier = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
|
|
pm_imr = intel_uncore_read(&dev_priv->uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
|
|
/*
|
|
* The equivalent to the PM ISR & IIR cannot be read
|
|
* without affecting the current state of the system
|
|
*/
|
|
pm_isr = 0;
|
|
pm_iir = 0;
|
|
} else if (GRAPHICS_VER(dev_priv) >= 8) {
|
|
pm_ier = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IER(2));
|
|
pm_imr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IMR(2));
|
|
pm_isr = intel_uncore_read(&dev_priv->uncore, GEN8_GT_ISR(2));
|
|
pm_iir = intel_uncore_read(&dev_priv->uncore, GEN8_GT_IIR(2));
|
|
} else {
|
|
pm_ier = intel_uncore_read(&dev_priv->uncore, GEN6_PMIER);
|
|
pm_imr = intel_uncore_read(&dev_priv->uncore, GEN6_PMIMR);
|
|
pm_isr = intel_uncore_read(&dev_priv->uncore, GEN6_PMISR);
|
|
pm_iir = intel_uncore_read(&dev_priv->uncore, GEN6_PMIIR);
|
|
}
|
|
pm_mask = intel_uncore_read(&dev_priv->uncore, GEN6_PMINTRMSK);
|
|
|
|
seq_printf(m, "Video Turbo Mode: %s\n",
|
|
yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
|
|
seq_printf(m, "HW control enabled: %s\n",
|
|
yesno(rpmodectl & GEN6_RP_ENABLE));
|
|
seq_printf(m, "SW control enabled: %s\n",
|
|
yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
|
|
GEN6_RP_MEDIA_SW_MODE));
|
|
|
|
seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
|
|
pm_ier, pm_imr, pm_mask);
|
|
if (GRAPHICS_VER(dev_priv) <= 10)
|
|
seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
|
|
pm_isr, pm_iir);
|
|
seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
|
|
rps->pm_intrmsk_mbz);
|
|
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
|
|
seq_printf(m, "Render p-state ratio: %d\n",
|
|
(gt_perf_status & (GRAPHICS_VER(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
|
|
seq_printf(m, "Render p-state VID: %d\n",
|
|
gt_perf_status & 0xff);
|
|
seq_printf(m, "Render p-state limit: %d\n",
|
|
rp_state_limits & 0xff);
|
|
seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
|
|
seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
|
|
seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
|
|
seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
|
|
seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
|
|
seq_printf(m, "CAGF: %dMHz\n", cagf);
|
|
seq_printf(m, "RP CUR UP EI: %d (%lldns)\n",
|
|
rpupei,
|
|
intel_gt_pm_interval_to_ns(&dev_priv->gt, rpupei));
|
|
seq_printf(m, "RP CUR UP: %d (%lldun)\n",
|
|
rpcurup,
|
|
intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurup));
|
|
seq_printf(m, "RP PREV UP: %d (%lldns)\n",
|
|
rpprevup,
|
|
intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup));
|
|
seq_printf(m, "Up threshold: %d%%\n",
|
|
rps->power.up_threshold);
|
|
|
|
seq_printf(m, "RP CUR DOWN EI: %d (%lldns)\n",
|
|
rpdownei,
|
|
intel_gt_pm_interval_to_ns(&dev_priv->gt,
|
|
rpdownei));
|
|
seq_printf(m, "RP CUR DOWN: %d (%lldns)\n",
|
|
rpcurdown,
|
|
intel_gt_pm_interval_to_ns(&dev_priv->gt,
|
|
rpcurdown));
|
|
seq_printf(m, "RP PREV DOWN: %d (%lldns)\n",
|
|
rpprevdown,
|
|
intel_gt_pm_interval_to_ns(&dev_priv->gt,
|
|
rpprevdown));
|
|
seq_printf(m, "Down threshold: %d%%\n",
|
|
rps->power.down_threshold);
|
|
|
|
max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
|
|
rp_state_cap >> 16) & 0xff;
|
|
max_freq *= (IS_GEN9_BC(dev_priv) ||
|
|
GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
|
|
seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
|
|
intel_gpu_freq(rps, max_freq));
|
|
|
|
max_freq = (rp_state_cap & 0xff00) >> 8;
|
|
max_freq *= (IS_GEN9_BC(dev_priv) ||
|
|
GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
|
|
seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
|
|
intel_gpu_freq(rps, max_freq));
|
|
|
|
max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
|
|
rp_state_cap >> 0) & 0xff;
|
|
max_freq *= (IS_GEN9_BC(dev_priv) ||
|
|
GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
|
|
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
|
|
intel_gpu_freq(rps, max_freq));
|
|
seq_printf(m, "Max overclocked frequency: %dMHz\n",
|
|
intel_gpu_freq(rps, rps->max_freq));
|
|
|
|
seq_printf(m, "Current freq: %d MHz\n",
|
|
intel_gpu_freq(rps, rps->cur_freq));
|
|
seq_printf(m, "Actual freq: %d MHz\n", cagf);
|
|
seq_printf(m, "Idle freq: %d MHz\n",
|
|
intel_gpu_freq(rps, rps->idle_freq));
|
|
seq_printf(m, "Min freq: %d MHz\n",
|
|
intel_gpu_freq(rps, rps->min_freq));
|
|
seq_printf(m, "Boost freq: %d MHz\n",
|
|
intel_gpu_freq(rps, rps->boost_freq));
|
|
seq_printf(m, "Max freq: %d MHz\n",
|
|
intel_gpu_freq(rps, rps->max_freq));
|
|
seq_printf(m,
|
|
"efficient (RPe) frequency: %d MHz\n",
|
|
intel_gpu_freq(rps, rps->efficient_freq));
|
|
} else {
|
|
seq_puts(m, "no P-state info available\n");
|
|
}
|
|
|
|
seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
|
|
seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
|
|
seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
|
|
|
|
intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
|
|
return 0;
|
|
}
|
|
|
|
static const char *swizzle_string(unsigned swizzle)
|
|
{
|
|
switch (swizzle) {
|
|
case I915_BIT_6_SWIZZLE_NONE:
|
|
return "none";
|
|
case I915_BIT_6_SWIZZLE_9:
|
|
return "bit9";
|
|
case I915_BIT_6_SWIZZLE_9_10:
|
|
return "bit9/bit10";
|
|
case I915_BIT_6_SWIZZLE_9_11:
|
|
return "bit9/bit11";
|
|
case I915_BIT_6_SWIZZLE_9_10_11:
|
|
return "bit9/bit10/bit11";
|
|
case I915_BIT_6_SWIZZLE_9_17:
|
|
return "bit9/bit17";
|
|
case I915_BIT_6_SWIZZLE_9_10_17:
|
|
return "bit9/bit10/bit17";
|
|
case I915_BIT_6_SWIZZLE_UNKNOWN:
|
|
return "unknown";
|
|
}
|
|
|
|
return "bug";
|
|
}
|
|
|
|
static int i915_swizzle_info(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_i915_private *dev_priv = node_to_i915(m->private);
|
|
struct intel_uncore *uncore = &dev_priv->uncore;
|
|
intel_wakeref_t wakeref;
|
|
|
|
seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
|
|
swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
|
|
seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
|
|
swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
|
|
|
|
if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
|
|
seq_puts(m, "L-shaped memory detected\n");
|
|
|
|
/* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */
|
|
if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
|
|
return 0;
|
|
|
|
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
|
|
|
|
if (IS_GRAPHICS_VER(dev_priv, 3, 4)) {
|
|
seq_printf(m, "DDC = 0x%08x\n",
|
|
intel_uncore_read(uncore, DCC));
|
|
seq_printf(m, "DDC2 = 0x%08x\n",
|
|
intel_uncore_read(uncore, DCC2));
|
|
seq_printf(m, "C0DRB3 = 0x%04x\n",
|
|
intel_uncore_read16(uncore, C0DRB3_BW));
|
|
seq_printf(m, "C1DRB3 = 0x%04x\n",
|
|
intel_uncore_read16(uncore, C1DRB3_BW));
|
|
} else if (GRAPHICS_VER(dev_priv) >= 6) {
|
|
seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
|
|
intel_uncore_read(uncore, MAD_DIMM_C0));
|
|
seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
|
|
intel_uncore_read(uncore, MAD_DIMM_C1));
|
|
seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
|
|
intel_uncore_read(uncore, MAD_DIMM_C2));
|
|
seq_printf(m, "TILECTL = 0x%08x\n",
|
|
intel_uncore_read(uncore, TILECTL));
|
|
if (GRAPHICS_VER(dev_priv) >= 8)
|
|
seq_printf(m, "GAMTARBMODE = 0x%08x\n",
|
|
intel_uncore_read(uncore, GAMTARBMODE));
|
|
else
|
|
seq_printf(m, "ARB_MODE = 0x%08x\n",
|
|
intel_uncore_read(uncore, ARB_MODE));
|
|
seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
|
|
intel_uncore_read(uncore, DISP_ARB_CTL));
|
|
}
|
|
|
|
intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_rps_boost_info(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_i915_private *dev_priv = node_to_i915(m->private);
|
|
struct intel_rps *rps = &dev_priv->gt.rps;
|
|
|
|
seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
|
|
seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
|
|
seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake));
|
|
seq_printf(m, "Boosts outstanding? %d\n",
|
|
atomic_read(&rps->num_waiters));
|
|
seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
|
|
seq_printf(m, "Frequency requested %d, actual %d\n",
|
|
intel_gpu_freq(rps, rps->cur_freq),
|
|
intel_rps_read_actual_frequency(rps));
|
|
seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
|
|
intel_gpu_freq(rps, rps->min_freq),
|
|
intel_gpu_freq(rps, rps->min_freq_softlimit),
|
|
intel_gpu_freq(rps, rps->max_freq_softlimit),
|
|
intel_gpu_freq(rps, rps->max_freq));
|
|
seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
|
|
intel_gpu_freq(rps, rps->idle_freq),
|
|
intel_gpu_freq(rps, rps->efficient_freq),
|
|
intel_gpu_freq(rps, rps->boost_freq));
|
|
|
|
seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_runtime_pm_status(struct seq_file *m, void *unused)
|
|
{
|
|
struct drm_i915_private *dev_priv = node_to_i915(m->private);
|
|
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
|
|
|
|
if (!HAS_RUNTIME_PM(dev_priv))
|
|
seq_puts(m, "Runtime power management not supported\n");
|
|
|
|
seq_printf(m, "Runtime power status: %s\n",
|
|
enableddisabled(!dev_priv->power_domains.init_wakeref));
|
|
|
|
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
|
|
seq_printf(m, "IRQs disabled: %s\n",
|
|
yesno(!intel_irqs_enabled(dev_priv)));
|
|
#ifdef CONFIG_PM
|
|
seq_printf(m, "Usage count: %d\n",
|
|
atomic_read(&dev_priv->drm.dev->power.usage_count));
|
|
#else
|
|
seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
|
|
#endif
|
|
seq_printf(m, "PCI device power state: %s [%d]\n",
|
|
pci_power_name(pdev->current_state),
|
|
pdev->current_state);
|
|
|
|
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) {
|
|
struct drm_printer p = drm_seq_file_printer(m);
|
|
|
|
print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_engine_info(struct seq_file *m, void *unused)
|
|
{
|
|
struct drm_i915_private *i915 = node_to_i915(m->private);
|
|
struct intel_engine_cs *engine;
|
|
intel_wakeref_t wakeref;
|
|
struct drm_printer p;
|
|
|
|
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
|
|
|
|
seq_printf(m, "GT awake? %s [%d], %llums\n",
|
|
yesno(i915->gt.awake),
|
|
atomic_read(&i915->gt.wakeref.count),
|
|
ktime_to_ms(intel_gt_get_awake_time(&i915->gt)));
|
|
seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
|
|
i915->gt.clock_frequency,
|
|
i915->gt.clock_period_ns);
|
|
|
|
p = drm_seq_file_printer(m);
|
|
for_each_uabi_engine(engine, i915)
|
|
intel_engine_dump(engine, &p, "%s\n", engine->name);
|
|
|
|
intel_gt_show_timelines(&i915->gt, &p, i915_request_show_with_schedule);
|
|
|
|
intel_runtime_pm_put(&i915->runtime_pm, wakeref);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_wa_registers(struct seq_file *m, void *unused)
|
|
{
|
|
struct drm_i915_private *i915 = node_to_i915(m->private);
|
|
struct intel_engine_cs *engine;
|
|
|
|
for_each_uabi_engine(engine, i915) {
|
|
const struct i915_wa_list *wal = &engine->ctx_wa_list;
|
|
const struct i915_wa *wa;
|
|
unsigned int count;
|
|
|
|
count = wal->count;
|
|
if (!count)
|
|
continue;
|
|
|
|
seq_printf(m, "%s: Workarounds applied: %u\n",
|
|
engine->name, count);
|
|
|
|
for (wa = wal->list; count--; wa++)
|
|
seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
|
|
i915_mmio_reg_offset(wa->reg),
|
|
wa->set, wa->clr);
|
|
|
|
seq_printf(m, "\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
i915_wedged_get(void *data, u64 *val)
|
|
{
|
|
struct drm_i915_private *i915 = data;
|
|
int ret = intel_gt_terminally_wedged(&i915->gt);
|
|
|
|
switch (ret) {
|
|
case -EIO:
|
|
*val = 1;
|
|
return 0;
|
|
case 0:
|
|
*val = 0;
|
|
return 0;
|
|
default:
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
static int
|
|
i915_wedged_set(void *data, u64 val)
|
|
{
|
|
struct drm_i915_private *i915 = data;
|
|
|
|
/* Flush any previous reset before applying for a new one */
|
|
wait_event(i915->gt.reset.queue,
|
|
!test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags));
|
|
|
|
intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE,
|
|
"Manually set wedged engine mask = %llx", val);
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
|
|
i915_wedged_get, i915_wedged_set,
|
|
"%llu\n");
|
|
|
|
static int
|
|
i915_perf_noa_delay_set(void *data, u64 val)
|
|
{
|
|
struct drm_i915_private *i915 = data;
|
|
|
|
/*
|
|
* This would lead to infinite waits as we're doing timestamp
|
|
* difference on the CS with only 32bits.
|
|
*/
|
|
if (intel_gt_ns_to_clock_interval(&i915->gt, val) > U32_MAX)
|
|
return -EINVAL;
|
|
|
|
atomic64_set(&i915->perf.noa_programming_delay, val);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
i915_perf_noa_delay_get(void *data, u64 *val)
|
|
{
|
|
struct drm_i915_private *i915 = data;
|
|
|
|
*val = atomic64_read(&i915->perf.noa_programming_delay);
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
|
|
i915_perf_noa_delay_get,
|
|
i915_perf_noa_delay_set,
|
|
"%llu\n");
|
|
|
|
#define DROP_UNBOUND BIT(0)
|
|
#define DROP_BOUND BIT(1)
|
|
#define DROP_RETIRE BIT(2)
|
|
#define DROP_ACTIVE BIT(3)
|
|
#define DROP_FREED BIT(4)
|
|
#define DROP_SHRINK_ALL BIT(5)
|
|
#define DROP_IDLE BIT(6)
|
|
#define DROP_RESET_ACTIVE BIT(7)
|
|
#define DROP_RESET_SEQNO BIT(8)
|
|
#define DROP_RCU BIT(9)
|
|
#define DROP_ALL (DROP_UNBOUND | \
|
|
DROP_BOUND | \
|
|
DROP_RETIRE | \
|
|
DROP_ACTIVE | \
|
|
DROP_FREED | \
|
|
DROP_SHRINK_ALL |\
|
|
DROP_IDLE | \
|
|
DROP_RESET_ACTIVE | \
|
|
DROP_RESET_SEQNO | \
|
|
DROP_RCU)
|
|
static int
|
|
i915_drop_caches_get(void *data, u64 *val)
|
|
{
|
|
*val = DROP_ALL;
|
|
|
|
return 0;
|
|
}
|
|
static int
|
|
gt_drop_caches(struct intel_gt *gt, u64 val)
|
|
{
|
|
int ret;
|
|
|
|
if (val & DROP_RESET_ACTIVE &&
|
|
wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT))
|
|
intel_gt_set_wedged(gt);
|
|
|
|
if (val & DROP_RETIRE)
|
|
intel_gt_retire_requests(gt);
|
|
|
|
if (val & (DROP_IDLE | DROP_ACTIVE)) {
|
|
ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (val & DROP_IDLE) {
|
|
ret = intel_gt_pm_wait_for_idle(gt);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt))
|
|
intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL);
|
|
|
|
if (val & DROP_FREED)
|
|
intel_gt_flush_buffer_pool(gt);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
i915_drop_caches_set(void *data, u64 val)
|
|
{
|
|
struct drm_i915_private *i915 = data;
|
|
int ret;
|
|
|
|
DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
|
|
val, val & DROP_ALL);
|
|
|
|
ret = gt_drop_caches(&i915->gt, val);
|
|
if (ret)
|
|
return ret;
|
|
|
|
fs_reclaim_acquire(GFP_KERNEL);
|
|
if (val & DROP_BOUND)
|
|
i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND);
|
|
|
|
if (val & DROP_UNBOUND)
|
|
i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
|
|
|
|
if (val & DROP_SHRINK_ALL)
|
|
i915_gem_shrink_all(i915);
|
|
fs_reclaim_release(GFP_KERNEL);
|
|
|
|
if (val & DROP_RCU)
|
|
rcu_barrier();
|
|
|
|
if (val & DROP_FREED)
|
|
i915_gem_drain_freed_objects(i915);
|
|
|
|
return 0;
|
|
}
|
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
|
|
i915_drop_caches_get, i915_drop_caches_set,
|
|
"0x%08llx\n");
|
|
|
|
static int i915_sseu_status(struct seq_file *m, void *unused)
|
|
{
|
|
struct drm_i915_private *i915 = node_to_i915(m->private);
|
|
struct intel_gt *gt = &i915->gt;
|
|
|
|
return intel_sseu_status(m, gt);
|
|
}
|
|
|
|
static int i915_forcewake_open(struct inode *inode, struct file *file)
|
|
{
|
|
struct drm_i915_private *i915 = inode->i_private;
|
|
struct intel_gt *gt = &i915->gt;
|
|
|
|
atomic_inc(>->user_wakeref);
|
|
intel_gt_pm_get(gt);
|
|
if (GRAPHICS_VER(i915) >= 6)
|
|
intel_uncore_forcewake_user_get(gt->uncore);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_forcewake_release(struct inode *inode, struct file *file)
|
|
{
|
|
struct drm_i915_private *i915 = inode->i_private;
|
|
struct intel_gt *gt = &i915->gt;
|
|
|
|
if (GRAPHICS_VER(i915) >= 6)
|
|
intel_uncore_forcewake_user_put(&i915->uncore);
|
|
intel_gt_pm_put(gt);
|
|
atomic_dec(>->user_wakeref);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct file_operations i915_forcewake_fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = i915_forcewake_open,
|
|
.release = i915_forcewake_release,
|
|
};
|
|
|
|
static const struct drm_info_list i915_debugfs_list[] = {
|
|
{"i915_capabilities", i915_capabilities, 0},
|
|
{"i915_gem_objects", i915_gem_object_info, 0},
|
|
{"i915_frequency_info", i915_frequency_info, 0},
|
|
{"i915_swizzle_info", i915_swizzle_info, 0},
|
|
{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
|
|
{"i915_engine_info", i915_engine_info, 0},
|
|
{"i915_wa_registers", i915_wa_registers, 0},
|
|
{"i915_sseu_status", i915_sseu_status, 0},
|
|
{"i915_rps_boost_info", i915_rps_boost_info, 0},
|
|
};
|
|
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
|
|
|
|
static const struct i915_debugfs_files {
|
|
const char *name;
|
|
const struct file_operations *fops;
|
|
} i915_debugfs_files[] = {
|
|
{"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
|
|
{"i915_wedged", &i915_wedged_fops},
|
|
{"i915_gem_drop_caches", &i915_drop_caches_fops},
|
|
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
|
|
{"i915_error_state", &i915_error_state_fops},
|
|
{"i915_gpu_info", &i915_gpu_info_fops},
|
|
#endif
|
|
};
|
|
|
|
void i915_debugfs_register(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct drm_minor *minor = dev_priv->drm.primary;
|
|
int i;
|
|
|
|
i915_debugfs_params(dev_priv);
|
|
|
|
debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
|
|
to_i915(minor->dev), &i915_forcewake_fops);
|
|
for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
|
|
debugfs_create_file(i915_debugfs_files[i].name,
|
|
S_IRUGO | S_IWUSR,
|
|
minor->debugfs_root,
|
|
to_i915(minor->dev),
|
|
i915_debugfs_files[i].fops);
|
|
}
|
|
|
|
drm_debugfs_create_files(i915_debugfs_list,
|
|
I915_DEBUGFS_ENTRIES,
|
|
minor->debugfs_root, minor);
|
|
}
|