mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
b65a948973
Jason Ekstrand requested a more efficient method than userptr+set-domain
to determine if the userptr object was backed by a complete set of pages
upon creation. To be more efficient than simply populating the userptr
using get_user_pages() (as done by the call to set-domain or execbuf),
we can walk the tree of vm_area_struct and check for gaps or vma not
backed by struct page (VM_PFNMAP). The question is how to handle
VM_MIXEDMAP which may be either struct page or pfn backed...
With discrete we are going to drop support for set_domain(), so offering
a way to probe the pages, without having to resort to dummy batches has
been requested.
v2:
- add new query param for the PROBE flag, so userspace can easily
check if the kernel supports it(Jason).
- use mmap_read_{lock, unlock}.
- add some kernel-doc.
v3:
- In the docs also mention that PROBE doesn't guarantee that the pages
will remain valid by the time they are actually used(Tvrtko).
- Add a small comment for the hole finding logic(Jason).
- Move the param next to all the other params which just return true.
Testcase: igt/gem_userptr_blits/probe
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723113405.427004-1-matthew.auld@intel.com
178 lines
4.8 KiB
C
178 lines
4.8 KiB
C
/*
|
|
* SPDX-License-Identifier: MIT
|
|
*/
|
|
|
|
#include "gem/i915_gem_mman.h"
|
|
#include "gt/intel_engine_user.h"
|
|
|
|
#include "i915_drv.h"
|
|
#include "i915_perf.h"
|
|
|
|
int i915_getparam_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct drm_i915_private *i915 = to_i915(dev);
|
|
struct pci_dev *pdev = to_pci_dev(dev->dev);
|
|
const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
|
|
drm_i915_getparam_t *param = data;
|
|
int value = 0;
|
|
|
|
switch (param->param) {
|
|
case I915_PARAM_IRQ_ACTIVE:
|
|
case I915_PARAM_ALLOW_BATCHBUFFER:
|
|
case I915_PARAM_LAST_DISPATCH:
|
|
case I915_PARAM_HAS_EXEC_CONSTANTS:
|
|
/* Reject all old ums/dri params. */
|
|
return -ENODEV;
|
|
case I915_PARAM_CHIPSET_ID:
|
|
value = pdev->device;
|
|
break;
|
|
case I915_PARAM_REVISION:
|
|
value = pdev->revision;
|
|
break;
|
|
case I915_PARAM_NUM_FENCES_AVAIL:
|
|
value = i915->ggtt.num_fences;
|
|
break;
|
|
case I915_PARAM_HAS_OVERLAY:
|
|
value = !!i915->overlay;
|
|
break;
|
|
case I915_PARAM_HAS_BSD:
|
|
value = !!intel_engine_lookup_user(i915,
|
|
I915_ENGINE_CLASS_VIDEO, 0);
|
|
break;
|
|
case I915_PARAM_HAS_BLT:
|
|
value = !!intel_engine_lookup_user(i915,
|
|
I915_ENGINE_CLASS_COPY, 0);
|
|
break;
|
|
case I915_PARAM_HAS_VEBOX:
|
|
value = !!intel_engine_lookup_user(i915,
|
|
I915_ENGINE_CLASS_VIDEO_ENHANCE, 0);
|
|
break;
|
|
case I915_PARAM_HAS_BSD2:
|
|
value = !!intel_engine_lookup_user(i915,
|
|
I915_ENGINE_CLASS_VIDEO, 1);
|
|
break;
|
|
case I915_PARAM_HAS_LLC:
|
|
value = HAS_LLC(i915);
|
|
break;
|
|
case I915_PARAM_HAS_WT:
|
|
value = HAS_WT(i915);
|
|
break;
|
|
case I915_PARAM_HAS_ALIASING_PPGTT:
|
|
value = INTEL_PPGTT(i915);
|
|
break;
|
|
case I915_PARAM_HAS_SEMAPHORES:
|
|
value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
|
|
break;
|
|
case I915_PARAM_HAS_SECURE_BATCHES:
|
|
value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
|
|
break;
|
|
case I915_PARAM_CMD_PARSER_VERSION:
|
|
value = i915_cmd_parser_get_version(i915);
|
|
break;
|
|
case I915_PARAM_SUBSLICE_TOTAL:
|
|
value = intel_sseu_subslice_total(sseu);
|
|
if (!value)
|
|
return -ENODEV;
|
|
break;
|
|
case I915_PARAM_EU_TOTAL:
|
|
value = sseu->eu_total;
|
|
if (!value)
|
|
return -ENODEV;
|
|
break;
|
|
case I915_PARAM_HAS_GPU_RESET:
|
|
value = i915->params.enable_hangcheck &&
|
|
intel_has_gpu_reset(&i915->gt);
|
|
if (value && intel_has_reset_engine(&i915->gt))
|
|
value = 2;
|
|
break;
|
|
case I915_PARAM_HAS_RESOURCE_STREAMER:
|
|
value = 0;
|
|
break;
|
|
case I915_PARAM_HAS_POOLED_EU:
|
|
value = HAS_POOLED_EU(i915);
|
|
break;
|
|
case I915_PARAM_MIN_EU_IN_POOL:
|
|
value = sseu->min_eu_in_pool;
|
|
break;
|
|
case I915_PARAM_HUC_STATUS:
|
|
value = intel_huc_check_status(&i915->gt.uc.huc);
|
|
if (value < 0)
|
|
return value;
|
|
break;
|
|
case I915_PARAM_MMAP_GTT_VERSION:
|
|
/* Though we've started our numbering from 1, and so class all
|
|
* earlier versions as 0, in effect their value is undefined as
|
|
* the ioctl will report EINVAL for the unknown param!
|
|
*/
|
|
value = i915_gem_mmap_gtt_version();
|
|
break;
|
|
case I915_PARAM_HAS_SCHEDULER:
|
|
value = i915->caps.scheduler;
|
|
break;
|
|
|
|
case I915_PARAM_MMAP_VERSION:
|
|
/* Remember to bump this if the version changes! */
|
|
case I915_PARAM_HAS_GEM:
|
|
case I915_PARAM_HAS_PAGEFLIPPING:
|
|
case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
|
|
case I915_PARAM_HAS_RELAXED_FENCING:
|
|
case I915_PARAM_HAS_COHERENT_RINGS:
|
|
case I915_PARAM_HAS_RELAXED_DELTA:
|
|
case I915_PARAM_HAS_GEN7_SOL_RESET:
|
|
case I915_PARAM_HAS_WAIT_TIMEOUT:
|
|
case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
|
|
case I915_PARAM_HAS_PINNED_BATCHES:
|
|
case I915_PARAM_HAS_EXEC_NO_RELOC:
|
|
case I915_PARAM_HAS_EXEC_HANDLE_LUT:
|
|
case I915_PARAM_HAS_COHERENT_PHYS_GTT:
|
|
case I915_PARAM_HAS_EXEC_SOFTPIN:
|
|
case I915_PARAM_HAS_EXEC_ASYNC:
|
|
case I915_PARAM_HAS_EXEC_FENCE:
|
|
case I915_PARAM_HAS_EXEC_CAPTURE:
|
|
case I915_PARAM_HAS_EXEC_BATCH_FIRST:
|
|
case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
|
|
case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
|
|
case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
|
|
case I915_PARAM_HAS_USERPTR_PROBE:
|
|
/* For the time being all of these are always true;
|
|
* if some supported hardware does not have one of these
|
|
* features this value needs to be provided from
|
|
* INTEL_INFO(), a feature macro, or similar.
|
|
*/
|
|
value = 1;
|
|
break;
|
|
case I915_PARAM_HAS_CONTEXT_ISOLATION:
|
|
value = intel_engines_has_context_isolation(i915);
|
|
break;
|
|
case I915_PARAM_SLICE_MASK:
|
|
value = sseu->slice_mask;
|
|
if (!value)
|
|
return -ENODEV;
|
|
break;
|
|
case I915_PARAM_SUBSLICE_MASK:
|
|
/* Only copy bits from the first slice */
|
|
memcpy(&value, sseu->subslice_mask,
|
|
min(sseu->ss_stride, (u8)sizeof(value)));
|
|
if (!value)
|
|
return -ENODEV;
|
|
break;
|
|
case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
|
|
value = i915->gt.clock_frequency;
|
|
break;
|
|
case I915_PARAM_MMAP_GTT_COHERENT:
|
|
value = INTEL_INFO(i915)->has_coherent_ggtt;
|
|
break;
|
|
case I915_PARAM_PERF_REVISION:
|
|
value = i915_perf_ioctl_version();
|
|
break;
|
|
default:
|
|
DRM_DEBUG("Unknown parameter %d\n", param->param);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (put_user(value, param->value))
|
|
return -EFAULT;
|
|
|
|
return 0;
|
|
}
|