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![Thomas Zimmermann](/assets/img/avatar_default.png)
Backmerging from drm/drm-next to the patches for AMD devices for v5.14. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
351 lines
7.1 KiB
C
351 lines
7.1 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2008-2018 Intel Corporation
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*/
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#ifndef _I915_GPU_ERROR_H_
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#define _I915_GPU_ERROR_H_
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#include <linux/atomic.h>
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#include <linux/kref.h>
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#include <linux/ktime.h>
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#include <linux/sched.h>
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#include <drm/drm_mm.h>
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#include "gt/intel_engine.h"
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#include "gt/intel_gt_types.h"
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#include "gt/uc/intel_uc_fw.h"
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#include "intel_device_info.h"
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#include "i915_gem.h"
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#include "i915_gem_gtt.h"
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#include "i915_params.h"
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#include "i915_scheduler.h"
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struct drm_i915_private;
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struct i915_vma_compress;
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struct intel_engine_capture_vma;
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struct intel_overlay_error_state;
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struct i915_vma_coredump {
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struct i915_vma_coredump *next;
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char name[20];
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u64 gtt_offset;
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u64 gtt_size;
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u32 gtt_page_sizes;
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int num_pages;
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int page_count;
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int unused;
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u32 *pages[];
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};
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struct i915_request_coredump {
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unsigned long flags;
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pid_t pid;
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u32 context;
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u32 seqno;
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u32 head;
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u32 tail;
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struct i915_sched_attr sched_attr;
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};
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struct intel_engine_coredump {
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const struct intel_engine_cs *engine;
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bool hung;
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bool simulated;
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u32 reset_count;
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/* position of active request inside the ring */
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u32 rq_head, rq_post, rq_tail;
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/* Register state */
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u32 ccid;
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u32 start;
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u32 tail;
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u32 head;
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u32 ctl;
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u32 mode;
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u32 hws;
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u32 ipeir;
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u32 ipehr;
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u32 esr;
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u32 bbstate;
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u32 instpm;
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u32 instps;
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u64 bbaddr;
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u64 acthd;
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u32 fault_reg;
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u64 faddr;
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u32 rc_psmi; /* sleep state */
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struct intel_instdone instdone;
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struct i915_gem_context_coredump {
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char comm[TASK_COMM_LEN];
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u64 total_runtime;
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u32 avg_runtime;
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pid_t pid;
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int active;
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int guilty;
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struct i915_sched_attr sched_attr;
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} context;
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struct i915_vma_coredump *vma;
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struct i915_request_coredump execlist[EXECLIST_MAX_PORTS];
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unsigned int num_ports;
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struct {
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u32 gfx_mode;
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union {
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u64 pdp[4];
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u32 pp_dir_base;
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};
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} vm_info;
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struct intel_engine_coredump *next;
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};
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struct intel_gt_coredump {
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const struct intel_gt *_gt;
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bool awake;
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bool simulated;
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struct intel_gt_info info;
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/* Generic register state */
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u32 eir;
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u32 pgtbl_er;
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u32 ier;
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u32 gtier[6], ngtier;
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u32 derrmr;
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u32 forcewake;
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u32 error; /* gen6+ */
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u32 err_int; /* gen7 */
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u32 fault_data0; /* gen8, gen9 */
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u32 fault_data1; /* gen8, gen9 */
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u32 done_reg;
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u32 gac_eco;
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u32 gam_ecochk;
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u32 gab_ctl;
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u32 gfx_mode;
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u32 gtt_cache;
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u32 aux_err; /* gen12 */
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u32 sfc_done[GEN12_SFC_DONE_MAX]; /* gen12 */
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u32 gam_done; /* gen12 */
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u32 nfence;
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u64 fence[I915_MAX_NUM_FENCES];
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struct intel_engine_coredump *engine;
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struct intel_uc_coredump {
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struct intel_uc_fw guc_fw;
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struct intel_uc_fw huc_fw;
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struct i915_vma_coredump *guc_log;
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} *uc;
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struct intel_gt_coredump *next;
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};
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struct i915_gpu_coredump {
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struct kref ref;
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ktime_t time;
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ktime_t boottime;
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ktime_t uptime;
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unsigned long capture;
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struct drm_i915_private *i915;
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struct intel_gt_coredump *gt;
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char error_msg[128];
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bool simulated;
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bool wakelock;
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bool suspended;
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int iommu;
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u32 reset_count;
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u32 suspend_count;
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struct intel_device_info device_info;
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struct intel_runtime_info runtime_info;
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struct intel_driver_caps driver_caps;
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struct i915_params params;
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struct intel_overlay_error_state *overlay;
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struct scatterlist *sgl, *fit;
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};
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struct i915_gpu_error {
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/* For reset and error_state handling. */
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spinlock_t lock;
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/* Protected by the above dev->gpu_error.lock. */
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struct i915_gpu_coredump *first_error;
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atomic_t pending_fb_pin;
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/** Number of times the device has been reset (global) */
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atomic_t reset_count;
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/** Number of times an engine has been reset */
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atomic_t reset_engine_count[I915_NUM_ENGINES];
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};
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struct drm_i915_error_state_buf {
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struct drm_i915_private *i915;
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struct scatterlist *sgl, *cur, *end;
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char *buf;
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size_t bytes;
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size_t size;
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loff_t iter;
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int err;
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};
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#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
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__printf(2, 3)
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void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
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struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt,
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intel_engine_mask_t engine_mask);
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void i915_capture_error_state(struct intel_gt *gt,
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intel_engine_mask_t engine_mask);
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struct i915_gpu_coredump *
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i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);
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struct intel_gt_coredump *
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intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp);
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struct intel_engine_coredump *
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intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp);
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struct intel_engine_capture_vma *
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intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
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struct i915_request *rq,
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gfp_t gfp);
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void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
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struct intel_engine_capture_vma *capture,
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struct i915_vma_compress *compress);
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struct i915_vma_compress *
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i915_vma_capture_prepare(struct intel_gt_coredump *gt);
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void i915_vma_capture_finish(struct intel_gt_coredump *gt,
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struct i915_vma_compress *compress);
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void i915_error_state_store(struct i915_gpu_coredump *error);
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static inline struct i915_gpu_coredump *
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i915_gpu_coredump_get(struct i915_gpu_coredump *gpu)
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{
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kref_get(&gpu->ref);
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return gpu;
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}
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ssize_t
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i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
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char *buf, loff_t offset, size_t count);
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void __i915_gpu_coredump_free(struct kref *kref);
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static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
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{
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if (gpu)
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kref_put(&gpu->ref, __i915_gpu_coredump_free);
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}
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struct i915_gpu_coredump *i915_first_error_state(struct drm_i915_private *i915);
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void i915_reset_error_state(struct drm_i915_private *i915);
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void i915_disable_error_state(struct drm_i915_private *i915, int err);
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#else
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static inline void
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i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask)
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{
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}
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static inline struct i915_gpu_coredump *
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i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
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{
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return NULL;
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}
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static inline struct intel_gt_coredump *
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intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp)
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{
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return NULL;
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}
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static inline struct intel_engine_coredump *
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intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp)
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{
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return NULL;
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}
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static inline struct intel_engine_capture_vma *
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intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
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struct i915_request *rq,
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gfp_t gfp)
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{
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return NULL;
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}
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static inline void
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intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
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struct intel_engine_capture_vma *capture,
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struct i915_vma_compress *compress)
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{
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}
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static inline struct i915_vma_compress *
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i915_vma_capture_prepare(struct intel_gt_coredump *gt)
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{
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return NULL;
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}
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static inline void
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i915_vma_capture_finish(struct intel_gt_coredump *gt,
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struct i915_vma_compress *compress)
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{
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}
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static inline void
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i915_error_state_store(struct i915_gpu_coredump *error)
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{
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}
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static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
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{
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}
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static inline struct i915_gpu_coredump *
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i915_first_error_state(struct drm_i915_private *i915)
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{
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return ERR_PTR(-ENODEV);
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}
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static inline void i915_reset_error_state(struct drm_i915_private *i915)
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{
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}
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static inline void i915_disable_error_state(struct drm_i915_private *i915,
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int err)
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{
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}
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#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
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#endif /* _I915_GPU_ERROR_H_ */
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