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379c9a24cc
Most if not all i.MX SoC's call a function which enables all UARTS.
This is a problem for users who need to re-parent the clock source,
because any attempt to change the parent results in an busy error
due to the fact that the clocks have been enabled already.
clk: failed to reparent uart1 to sys_pll1_80m: -16
Instead of pre-initializing all UARTS, scan the device tree to see
which UART clocks are associated to stdout, and only enable those
UART clocks if it's needed early. This will move initialization of
the remaining clocks until after the parenting of the clocks.
When the clocks are shutdown, this mechanism will also disable any
clocks that were pre-initialized.
Fixes: 9461f7b33d ("clk: fix CLK_SET_RATE_GATE with clock rate protection")
Suggested-by: Aisheng Dong <aisheng.dong@nxp.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
251 lines
11 KiB
C
251 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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*/
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/err.h>
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#include <soc/imx/revision.h>
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#include <soc/imx/timer.h>
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#include <asm/irq.h>
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#include "clk.h"
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#define MX35_CCM_BASE_ADDR 0x53f80000
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#define MX35_GPT1_BASE_ADDR 0x53f90000
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#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
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#define MXC_CCM_PDR0 0x04
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#define MX35_CCM_PDR2 0x0c
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#define MX35_CCM_PDR3 0x10
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#define MX35_CCM_PDR4 0x14
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#define MX35_CCM_MPCTL 0x1c
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#define MX35_CCM_PPCTL 0x20
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#define MX35_CCM_CGR0 0x2c
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#define MX35_CCM_CGR1 0x30
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#define MX35_CCM_CGR2 0x34
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#define MX35_CCM_CGR3 0x38
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struct arm_ahb_div {
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unsigned char arm, ahb, sel;
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};
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static struct arm_ahb_div clk_consumer[] = {
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{ .arm = 1, .ahb = 4, .sel = 0},
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{ .arm = 1, .ahb = 3, .sel = 1},
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{ .arm = 2, .ahb = 2, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 4, .ahb = 1, .sel = 0},
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{ .arm = 1, .ahb = 5, .sel = 0},
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{ .arm = 1, .ahb = 8, .sel = 0},
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{ .arm = 1, .ahb = 6, .sel = 1},
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{ .arm = 2, .ahb = 4, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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{ .arm = 4, .ahb = 2, .sel = 0},
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{ .arm = 0, .ahb = 0, .sel = 0},
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};
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static char hsp_div_532[] = { 4, 8, 3, 0 };
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static char hsp_div_400[] = { 3, 6, 3, 0 };
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static struct clk_onecell_data clk_data;
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static const char *std_sel[] = {"ppll", "arm"};
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static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
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enum mx35_clks {
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/* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb,
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/* 9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div,
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/* 15 */ esdhc_sel, esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel,
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/* 20 */ spdif_div_pre, spdif_div_post, ssi_sel, ssi1_div_pre,
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/* 24 */ ssi1_div_post, ssi2_div_pre, ssi2_div_post, usb_sel, usb_div,
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/* 29 */ nfc_div, asrc_gate, pata_gate, audmux_gate, can1_gate,
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/* 34 */ can2_gate, cspi1_gate, cspi2_gate, ect_gate, edio_gate,
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/* 39 */ emi_gate, epit1_gate, epit2_gate, esai_gate, esdhc1_gate,
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/* 44 */ esdhc2_gate, esdhc3_gate, fec_gate, gpio1_gate, gpio2_gate,
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/* 49 */ gpio3_gate, gpt_gate, i2c1_gate, i2c2_gate, i2c3_gate,
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/* 54 */ iomuxc_gate, ipu_gate, kpp_gate, mlb_gate, mshc_gate,
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/* 59 */ owire_gate, pwm_gate, rngc_gate, rtc_gate, rtic_gate, scc_gate,
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/* 65 */ sdma_gate, spba_gate, spdif_gate, ssi1_gate, ssi2_gate,
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/* 70 */ uart1_gate, uart2_gate, uart3_gate, usbotg_gate, wdog_gate,
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/* 75 */ max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
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/* 81 */ gpu2d_gate, ckil, clk_max
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};
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static struct clk *clk[clk_max];
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static void __init _mx35_clocks_init(void)
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{
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void __iomem *base;
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u32 pdr0, consumer_sel, hsp_sel;
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struct arm_ahb_div *aad;
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unsigned char *hsp_div;
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base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K);
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BUG_ON(!base);
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pdr0 = __raw_readl(base + MXC_CCM_PDR0);
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consumer_sel = (pdr0 >> 16) & 0xf;
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aad = &clk_consumer[consumer_sel];
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if (!aad->arm) {
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pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel);
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/*
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* We are basically stuck. Continue with a default entry and hope we
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* get far enough to actually show the above message
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*/
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aad = &clk_consumer[0];
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}
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clk[ckih] = imx_clk_fixed("ckih", 24000000);
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clk[ckil] = imx_clk_fixed("ckil", 32768);
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clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL);
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clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL);
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clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4);
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if (aad->sel)
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clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm);
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else
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clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm);
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if (clk_get_rate(clk[arm]) > 400000000)
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hsp_div = hsp_div_532;
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else
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hsp_div = hsp_div_400;
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hsp_sel = (pdr0 >> 20) & 0x3;
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if (!hsp_div[hsp_sel]) {
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pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel);
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hsp_sel = 0;
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}
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clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]);
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clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);
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clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
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clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6);
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clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3);
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clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel));
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clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel));
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clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6);
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clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
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clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6);
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clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6);
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clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6);
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clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel));
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clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */
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clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6);
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clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel));
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clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3);
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clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6);
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clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3);
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clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6);
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clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel));
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clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6);
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clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
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clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel));
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clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6);
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clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0);
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clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2);
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clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4);
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clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6);
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clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8);
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clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10);
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clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12);
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clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14);
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clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16);
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clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18);
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clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20);
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clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22);
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clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24);
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clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26);
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clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28);
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clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30);
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clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0);
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clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2);
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clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4);
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clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6);
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clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8);
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clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10);
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clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12);
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clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14);
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clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16);
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clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18);
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clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20);
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clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22);
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clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24);
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clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26);
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clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28);
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clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30);
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clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0);
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clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2);
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clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4);
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clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6);
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clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8);
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clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10);
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clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12);
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clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14);
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clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16);
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clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18);
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clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20);
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clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22);
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clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24);
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clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
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clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
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clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0);
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clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2);
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clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4);
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imx_check_clocks(clk, ARRAY_SIZE(clk));
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clk_prepare_enable(clk[spba_gate]);
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clk_prepare_enable(clk[gpio1_gate]);
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clk_prepare_enable(clk[gpio2_gate]);
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clk_prepare_enable(clk[gpio3_gate]);
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clk_prepare_enable(clk[iim_gate]);
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clk_prepare_enable(clk[emi_gate]);
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clk_prepare_enable(clk[max_gate]);
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clk_prepare_enable(clk[iomuxc_gate]);
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/*
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* SCC is needed to boot via mmc after a watchdog reset. The clock code
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* before conversion to common clk also enabled UART1 (which isn't
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* handled here and not needed for mmc) and IIM (which is enabled
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* unconditionally above).
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*/
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clk_prepare_enable(clk[scc_gate]);
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imx_register_uart_clocks(4);
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imx_print_silicon_rev("i.MX35", mx35_revision());
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}
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static void __init mx35_clocks_init_dt(struct device_node *ccm_node)
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{
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_mx35_clocks_init();
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
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}
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CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);
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