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2c9bce5b49
This change updates the 3ware drivers (3w-xxxx, 3w-9xxx, 3w-sas) email addresses from linuxraid@lsi.com to aradford@gmail.com, since the old email address doesn't exist. This patch was updated to remove www.lsi.com text. [mkp: applied by hand] Signed-off-by: Adam Radford <aradford@gmail.com> Acked-by: Sumit Saxena <sumit.saxena@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
389 lines
14 KiB
C
389 lines
14 KiB
C
/*
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3w-sas.h -- LSI 3ware SAS/SATA-RAID Controller device driver for Linux.
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Written By: Adam Radford <aradford@gmail.com>
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Copyright (C) 2009 LSI Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; version 2 of the License.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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NO WARRANTY
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THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
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CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
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LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
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MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
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solely responsible for determining the appropriateness of using and
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distributing the Program and assumes all risks associated with its
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exercise of rights under this Agreement, including but not limited to
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the risks and costs of program errors, damage to or loss of data,
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programs or equipment, and unavailability or interruption of operations.
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DISCLAIMER OF LIABILITY
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NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
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HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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Bugs/Comments/Suggestions should be mailed to:
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aradford@gmail.com
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*/
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#ifndef _3W_SAS_H
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#define _3W_SAS_H
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/* AEN severity table */
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static char *twl_aen_severity_table[] =
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{
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"None", "ERROR", "WARNING", "INFO", "DEBUG", NULL
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};
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/* Liberator register offsets */
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#define TWL_STATUS 0x0 /* Status */
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#define TWL_HIBDB 0x20 /* Inbound doorbell */
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#define TWL_HISTAT 0x30 /* Host interrupt status */
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#define TWL_HIMASK 0x34 /* Host interrupt mask */
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#define TWL_HOBDB 0x9C /* Outbound doorbell */
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#define TWL_HOBDBC 0xA0 /* Outbound doorbell clear */
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#define TWL_SCRPD3 0xBC /* Scratchpad */
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#define TWL_HIBQPL 0xC0 /* Host inbound Q low */
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#define TWL_HIBQPH 0xC4 /* Host inbound Q high */
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#define TWL_HOBQPL 0xC8 /* Host outbound Q low */
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#define TWL_HOBQPH 0xCC /* Host outbound Q high */
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#define TWL_HISTATUS_VALID_INTERRUPT 0xC
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#define TWL_HISTATUS_ATTENTION_INTERRUPT 0x4
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#define TWL_HISTATUS_RESPONSE_INTERRUPT 0x8
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#define TWL_STATUS_OVERRUN_SUBMIT 0x2000
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#define TWL_ISSUE_SOFT_RESET 0x100
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#define TWL_CONTROLLER_READY 0x2000
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#define TWL_DOORBELL_CONTROLLER_ERROR 0x200000
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#define TWL_DOORBELL_ATTENTION_INTERRUPT 0x40000
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#define TWL_PULL_MODE 0x1
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/* Command packet opcodes used by the driver */
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#define TW_OP_INIT_CONNECTION 0x1
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#define TW_OP_GET_PARAM 0x12
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#define TW_OP_SET_PARAM 0x13
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#define TW_OP_EXECUTE_SCSI 0x10
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/* Asynchronous Event Notification (AEN) codes used by the driver */
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#define TW_AEN_QUEUE_EMPTY 0x0000
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#define TW_AEN_SOFT_RESET 0x0001
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#define TW_AEN_SYNC_TIME_WITH_HOST 0x031
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#define TW_AEN_SEVERITY_ERROR 0x1
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#define TW_AEN_SEVERITY_DEBUG 0x4
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#define TW_AEN_NOT_RETRIEVED 0x1
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/* Command state defines */
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#define TW_S_INITIAL 0x1 /* Initial state */
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#define TW_S_STARTED 0x2 /* Id in use */
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#define TW_S_POSTED 0x4 /* Posted to the controller */
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#define TW_S_COMPLETED 0x8 /* Completed by isr */
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#define TW_S_FINISHED 0x10 /* I/O completely done */
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/* Compatibility defines */
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#define TW_9750_ARCH_ID 10
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#define TW_CURRENT_DRIVER_SRL 40
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#define TW_CURRENT_DRIVER_BUILD 0
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#define TW_CURRENT_DRIVER_BRANCH 0
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/* Misc defines */
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#define TW_SECTOR_SIZE 512
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#define TW_MAX_UNITS 32
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#define TW_INIT_MESSAGE_CREDITS 0x100
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#define TW_INIT_COMMAND_PACKET_SIZE 0x3
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#define TW_INIT_COMMAND_PACKET_SIZE_EXTENDED 0x6
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#define TW_EXTENDED_INIT_CONNECT 0x2
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#define TW_BASE_FW_SRL 24
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#define TW_BASE_FW_BRANCH 0
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#define TW_BASE_FW_BUILD 1
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#define TW_Q_LENGTH 256
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#define TW_Q_START 0
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#define TW_MAX_SLOT 32
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#define TW_MAX_RESET_TRIES 2
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#define TW_MAX_CMDS_PER_LUN 254
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#define TW_MAX_AEN_DRAIN 255
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#define TW_IN_RESET 2
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#define TW_USING_MSI 3
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#define TW_IN_ATTENTION_LOOP 4
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#define TW_MAX_SECTORS 256
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#define TW_MAX_CDB_LEN 16
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#define TW_IOCTL_CHRDEV_TIMEOUT 60 /* 60 seconds */
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#define TW_IOCTL_CHRDEV_FREE -1
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#define TW_COMMAND_OFFSET 128 /* 128 bytes */
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#define TW_VERSION_TABLE 0x0402
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#define TW_TIMEKEEP_TABLE 0x040A
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#define TW_INFORMATION_TABLE 0x0403
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#define TW_PARAM_FWVER 3
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#define TW_PARAM_FWVER_LENGTH 16
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#define TW_PARAM_BIOSVER 4
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#define TW_PARAM_BIOSVER_LENGTH 16
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#define TW_PARAM_MODEL 8
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#define TW_PARAM_MODEL_LENGTH 16
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#define TW_PARAM_PHY_SUMMARY_TABLE 1
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#define TW_PARAM_PHYCOUNT 2
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#define TW_PARAM_PHYCOUNT_LENGTH 1
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#define TW_IOCTL_FIRMWARE_PASS_THROUGH 0x108 // Used by smartmontools
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#define TW_ALLOCATION_LENGTH 128
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#define TW_SENSE_DATA_LENGTH 18
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#define TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x10a
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#define TW_ERROR_INVALID_FIELD_IN_CDB 0x10d
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#define TW_ERROR_UNIT_OFFLINE 0x128
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#define TW_MESSAGE_SOURCE_CONTROLLER_ERROR 3
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#define TW_MESSAGE_SOURCE_CONTROLLER_EVENT 4
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#define TW_DRIVER 6
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#ifndef PCI_DEVICE_ID_3WARE_9750
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#define PCI_DEVICE_ID_3WARE_9750 0x1010
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#endif
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/* Bitmask macros to eliminate bitfields */
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/* opcode: 5, reserved: 3 */
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#define TW_OPRES_IN(x,y) ((x << 5) | (y & 0x1f))
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#define TW_OP_OUT(x) (x & 0x1f)
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/* opcode: 5, sgloffset: 3 */
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#define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
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#define TW_SGL_OUT(x) ((x >> 5) & 0x7)
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/* severity: 3, reserved: 5 */
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#define TW_SEV_OUT(x) (x & 0x7)
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/* not_mfa: 1, reserved: 7, status: 8, request_id: 16 */
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#define TW_RESID_OUT(x) ((x >> 16) & 0xffff)
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#define TW_NOTMFA_OUT(x) (x & 0x1)
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/* request_id: 12, lun: 4 */
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#define TW_REQ_LUN_IN(lun, request_id) (((lun << 12) & 0xf000) | (request_id & 0xfff))
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#define TW_LUN_OUT(lun) ((lun >> 12) & 0xf)
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/* Register access macros */
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#define TWL_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_STATUS)
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#define TWL_HOBQPL_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBQPL)
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#define TWL_HOBQPH_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBQPH)
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#define TWL_HOBDB_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBDB)
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#define TWL_HOBDBC_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HOBDBC)
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#define TWL_HIMASK_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIMASK)
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#define TWL_HISTAT_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HISTAT)
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#define TWL_HIBQPH_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIBQPH)
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#define TWL_HIBQPL_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIBQPL)
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#define TWL_HIBDB_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_HIBDB)
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#define TWL_SCRPD3_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + TWL_SCRPD3)
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#define TWL_MASK_INTERRUPTS(x) (writel(~0, TWL_HIMASK_REG_ADDR(tw_dev)))
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#define TWL_UNMASK_INTERRUPTS(x) (writel(~TWL_HISTATUS_VALID_INTERRUPT, TWL_HIMASK_REG_ADDR(tw_dev)))
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#define TWL_CLEAR_DB_INTERRUPT(x) (writel(~0, TWL_HOBDBC_REG_ADDR(tw_dev)))
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#define TWL_SOFT_RESET(x) (writel(TWL_ISSUE_SOFT_RESET, TWL_HIBDB_REG_ADDR(tw_dev)))
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/* Macros */
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#define TW_PRINTK(h,a,b,c) { \
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if (h) \
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printk(KERN_WARNING "3w-sas: scsi%d: ERROR: (0x%02X:0x%04X): %s.\n",h->host_no,a,b,c); \
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else \
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printk(KERN_WARNING "3w-sas: ERROR: (0x%02X:0x%04X): %s.\n",a,b,c); \
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}
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#define TW_MAX_LUNS 16
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#define TW_COMMAND_SIZE (sizeof(dma_addr_t) > 4 ? 6 : 4)
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#define TW_LIBERATOR_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 46 : 92)
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#define TW_LIBERATOR_MAX_SGL_LENGTH_OLD (sizeof(dma_addr_t) > 4 ? 47 : 94)
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#define TW_PADDING_LENGTH_LIBERATOR 136
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#define TW_PADDING_LENGTH_LIBERATOR_OLD 132
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#define TW_CPU_TO_SGL(x) (sizeof(dma_addr_t) > 4 ? cpu_to_le64(x) : cpu_to_le32(x))
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#pragma pack(1)
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/* SGL entry */
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typedef struct TAG_TW_SG_Entry_ISO {
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dma_addr_t address;
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dma_addr_t length;
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} TW_SG_Entry_ISO;
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/* Old Command Packet with ISO SGL */
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typedef struct TW_Command {
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unsigned char opcode__sgloffset;
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unsigned char size;
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unsigned char request_id;
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unsigned char unit__hostid;
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/* Second DWORD */
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unsigned char status;
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unsigned char flags;
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union {
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unsigned short block_count;
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unsigned short parameter_count;
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} byte6_offset;
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union {
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struct {
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u32 lba;
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TW_SG_Entry_ISO sgl[TW_LIBERATOR_MAX_SGL_LENGTH_OLD];
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unsigned char padding[TW_PADDING_LENGTH_LIBERATOR_OLD];
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} io;
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struct {
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TW_SG_Entry_ISO sgl[TW_LIBERATOR_MAX_SGL_LENGTH_OLD];
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u32 padding;
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unsigned char padding2[TW_PADDING_LENGTH_LIBERATOR_OLD];
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} param;
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} byte8_offset;
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} TW_Command;
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/* New Command Packet with ISO SGL */
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typedef struct TAG_TW_Command_Apache {
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unsigned char opcode__reserved;
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unsigned char unit;
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unsigned short request_id__lunl;
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unsigned char status;
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unsigned char sgl_offset;
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unsigned short sgl_entries__lunh;
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unsigned char cdb[16];
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TW_SG_Entry_ISO sg_list[TW_LIBERATOR_MAX_SGL_LENGTH];
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unsigned char padding[TW_PADDING_LENGTH_LIBERATOR];
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} TW_Command_Apache;
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/* New command packet header */
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typedef struct TAG_TW_Command_Apache_Header {
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unsigned char sense_data[TW_SENSE_DATA_LENGTH];
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struct {
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char reserved[4];
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unsigned short error;
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unsigned char padding;
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unsigned char severity__reserved;
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} status_block;
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unsigned char err_specific_desc[98];
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struct {
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unsigned char size_header;
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unsigned short request_id;
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unsigned char size_sense;
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} header_desc;
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} TW_Command_Apache_Header;
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/* This struct is a union of the 2 command packets */
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typedef struct TAG_TW_Command_Full {
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TW_Command_Apache_Header header;
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union {
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TW_Command oldcommand;
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TW_Command_Apache newcommand;
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} command;
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} TW_Command_Full;
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/* Initconnection structure */
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typedef struct TAG_TW_Initconnect {
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unsigned char opcode__reserved;
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unsigned char size;
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unsigned char request_id;
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unsigned char res2;
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unsigned char status;
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unsigned char flags;
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unsigned short message_credits;
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u32 features;
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unsigned short fw_srl;
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unsigned short fw_arch_id;
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unsigned short fw_branch;
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unsigned short fw_build;
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u32 result;
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} TW_Initconnect;
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/* Event info structure */
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typedef struct TAG_TW_Event
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{
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unsigned int sequence_id;
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unsigned int time_stamp_sec;
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unsigned short aen_code;
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unsigned char severity;
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unsigned char retrieved;
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unsigned char repeat_count;
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unsigned char parameter_len;
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unsigned char parameter_data[98];
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} TW_Event;
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typedef struct TAG_TW_Ioctl_Driver_Command {
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unsigned int control_code;
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unsigned int status;
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unsigned int unique_id;
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unsigned int sequence_id;
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unsigned int os_specific;
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unsigned int buffer_length;
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} TW_Ioctl_Driver_Command;
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typedef struct TAG_TW_Ioctl_Apache {
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TW_Ioctl_Driver_Command driver_command;
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char padding[488];
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TW_Command_Full firmware_command;
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char data_buffer[1];
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} TW_Ioctl_Buf_Apache;
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/* GetParam descriptor */
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typedef struct {
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unsigned short table_id;
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unsigned short parameter_id;
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unsigned short parameter_size_bytes;
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unsigned short actual_parameter_size_bytes;
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unsigned char data[1];
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} TW_Param_Apache;
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/* Compatibility information structure */
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typedef struct TAG_TW_Compatibility_Info
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{
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char driver_version[32];
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unsigned short working_srl;
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unsigned short working_branch;
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unsigned short working_build;
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unsigned short driver_srl_high;
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unsigned short driver_branch_high;
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unsigned short driver_build_high;
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unsigned short driver_srl_low;
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unsigned short driver_branch_low;
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unsigned short driver_build_low;
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unsigned short fw_on_ctlr_srl;
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unsigned short fw_on_ctlr_branch;
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unsigned short fw_on_ctlr_build;
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} TW_Compatibility_Info;
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#pragma pack()
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typedef struct TAG_TW_Device_Extension {
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void __iomem *base_addr;
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unsigned long *generic_buffer_virt[TW_Q_LENGTH];
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dma_addr_t generic_buffer_phys[TW_Q_LENGTH];
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TW_Command_Full *command_packet_virt[TW_Q_LENGTH];
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dma_addr_t command_packet_phys[TW_Q_LENGTH];
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TW_Command_Apache_Header *sense_buffer_virt[TW_Q_LENGTH];
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dma_addr_t sense_buffer_phys[TW_Q_LENGTH];
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struct pci_dev *tw_pci_dev;
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struct scsi_cmnd *srb[TW_Q_LENGTH];
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unsigned char free_queue[TW_Q_LENGTH];
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unsigned char free_head;
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unsigned char free_tail;
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int state[TW_Q_LENGTH];
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unsigned int posted_request_count;
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unsigned int max_posted_request_count;
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unsigned int max_sgl_entries;
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unsigned int sgl_entries;
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unsigned int num_resets;
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unsigned int sector_count;
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unsigned int max_sector_count;
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unsigned int aen_count;
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struct Scsi_Host *host;
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long flags;
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TW_Event *event_queue[TW_Q_LENGTH];
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unsigned char error_index;
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unsigned int error_sequence_id;
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int chrdev_request_id;
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wait_queue_head_t ioctl_wqueue;
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struct mutex ioctl_lock;
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TW_Compatibility_Info tw_compat_info;
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char online;
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} TW_Device_Extension;
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#endif /* _3W_SAS_H */
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