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![Chengchang Tang](/assets/img/avatar_default.png)
HIP06 is no longer supported. In order to reduce unnecessary maintenance, the code of HIP06 is removed. Link: https://lore.kernel.org/r/20211220130558.61585-1-liangwenpeng@huawei.com Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com> Reviewed-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
1014 lines
26 KiB
C
1014 lines
26 KiB
C
/*
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* Copyright (c) 2016 Hisilicon Limited.
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* Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/acpi.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <rdma/ib_addr.h>
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#include <rdma/ib_smi.h>
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#include <rdma/ib_user_verbs.h>
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#include <rdma/ib_cache.h>
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#include "hns_roce_common.h"
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#include "hns_roce_device.h"
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#include "hns_roce_hem.h"
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static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port,
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const u8 *addr)
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{
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u8 phy_port;
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u32 i;
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if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
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return 0;
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if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
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return 0;
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for (i = 0; i < ETH_ALEN; i++)
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hr_dev->dev_addr[port][i] = addr[i];
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phy_port = hr_dev->iboe.phy_port[port];
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return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
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}
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static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
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u32 port = attr->port_num - 1;
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int ret;
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if (port >= hr_dev->caps.num_ports)
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return -EINVAL;
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ret = hr_dev->hw->set_gid(hr_dev, attr->index, &attr->gid, attr);
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return ret;
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}
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static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
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u32 port = attr->port_num - 1;
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int ret;
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if (port >= hr_dev->caps.num_ports)
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return -EINVAL;
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ret = hr_dev->hw->set_gid(hr_dev, attr->index, NULL, NULL);
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return ret;
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}
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static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port,
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unsigned long event)
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{
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struct device *dev = hr_dev->dev;
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struct net_device *netdev;
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int ret = 0;
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netdev = hr_dev->iboe.netdevs[port];
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if (!netdev) {
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dev_err(dev, "Can't find netdev on port(%u)!\n", port);
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return -ENODEV;
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}
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switch (event) {
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case NETDEV_UP:
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case NETDEV_CHANGE:
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case NETDEV_REGISTER:
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case NETDEV_CHANGEADDR:
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ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
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break;
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case NETDEV_DOWN:
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/*
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* In v1 engine, only support all ports closed together.
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*/
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break;
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default:
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dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
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break;
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}
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return ret;
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}
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static int hns_roce_netdev_event(struct notifier_block *self,
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unsigned long event, void *ptr)
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{
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struct net_device *dev = netdev_notifier_info_to_dev(ptr);
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struct hns_roce_ib_iboe *iboe = NULL;
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struct hns_roce_dev *hr_dev = NULL;
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int ret;
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u32 port;
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hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
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iboe = &hr_dev->iboe;
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for (port = 0; port < hr_dev->caps.num_ports; port++) {
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if (dev == iboe->netdevs[port]) {
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ret = handle_en_event(hr_dev, port, event);
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if (ret)
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return NOTIFY_DONE;
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break;
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}
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}
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return NOTIFY_DONE;
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}
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static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
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{
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int ret;
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u8 i;
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for (i = 0; i < hr_dev->caps.num_ports; i++) {
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ret = hns_roce_set_mac(hr_dev, i,
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hr_dev->iboe.netdevs[i]->dev_addr);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int hns_roce_query_device(struct ib_device *ib_dev,
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struct ib_device_attr *props,
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struct ib_udata *uhw)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
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memset(props, 0, sizeof(*props));
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props->fw_ver = hr_dev->caps.fw_ver;
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props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
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props->max_mr_size = (u64)(~(0ULL));
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props->page_size_cap = hr_dev->caps.page_size_cap;
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props->vendor_id = hr_dev->vendor_id;
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props->vendor_part_id = hr_dev->vendor_part_id;
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props->hw_ver = hr_dev->hw_rev;
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props->max_qp = hr_dev->caps.num_qps;
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props->max_qp_wr = hr_dev->caps.max_wqes;
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props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
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IB_DEVICE_RC_RNR_NAK_GEN;
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props->max_send_sge = hr_dev->caps.max_sq_sg;
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props->max_recv_sge = hr_dev->caps.max_rq_sg;
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props->max_sge_rd = 1;
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props->max_cq = hr_dev->caps.num_cqs;
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props->max_cqe = hr_dev->caps.max_cqes;
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props->max_mr = hr_dev->caps.num_mtpts;
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props->max_pd = hr_dev->caps.num_pds;
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props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
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props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
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props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
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IB_ATOMIC_HCA : IB_ATOMIC_NONE;
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props->max_pkeys = 1;
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props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
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if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
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props->max_srq = hr_dev->caps.num_srqs;
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props->max_srq_wr = hr_dev->caps.max_srq_wrs;
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props->max_srq_sge = hr_dev->caps.max_srq_sges;
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}
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if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR &&
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hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
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props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
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props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
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}
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if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
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props->device_cap_flags |= IB_DEVICE_XRC;
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return 0;
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}
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static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num,
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struct ib_port_attr *props)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
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struct device *dev = hr_dev->dev;
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struct net_device *net_dev;
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unsigned long flags;
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enum ib_mtu mtu;
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u32 port;
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port = port_num - 1;
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/* props being zeroed by the caller, avoid zeroing it here */
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props->max_mtu = hr_dev->caps.max_mtu;
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props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
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props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
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IB_PORT_VENDOR_CLASS_SUP |
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IB_PORT_BOOT_MGMT_SUP;
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props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
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props->pkey_tbl_len = 1;
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props->active_width = IB_WIDTH_4X;
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props->active_speed = 1;
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spin_lock_irqsave(&hr_dev->iboe.lock, flags);
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net_dev = hr_dev->iboe.netdevs[port];
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if (!net_dev) {
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spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
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dev_err(dev, "Find netdev %u failed!\n", port);
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return -EINVAL;
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}
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mtu = iboe_get_mtu(net_dev->mtu);
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props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
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props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
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IB_PORT_ACTIVE :
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IB_PORT_DOWN;
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props->phys_state = props->state == IB_PORT_ACTIVE ?
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IB_PORT_PHYS_STATE_LINK_UP :
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IB_PORT_PHYS_STATE_DISABLED;
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spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
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return 0;
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}
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static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
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u32 port_num)
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{
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return IB_LINK_LAYER_ETHERNET;
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}
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static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index,
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u16 *pkey)
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{
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if (index > 0)
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return -EINVAL;
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*pkey = PKEY_ID;
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return 0;
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}
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static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
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struct ib_device_modify *props)
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{
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unsigned long flags;
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if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
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return -EOPNOTSUPP;
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if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
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spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
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memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
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spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
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}
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return 0;
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}
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struct hns_user_mmap_entry *
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hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
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size_t length,
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enum hns_roce_mmap_type mmap_type)
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{
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struct hns_user_mmap_entry *entry;
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int ret;
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entry = kzalloc(sizeof(*entry), GFP_KERNEL);
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if (!entry)
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return NULL;
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entry->address = address;
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entry->mmap_type = mmap_type;
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switch (mmap_type) {
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/* pgoff 0 must be used by DB for compatibility */
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case HNS_ROCE_MMAP_TYPE_DB:
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ret = rdma_user_mmap_entry_insert_exact(
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ucontext, &entry->rdma_entry, length, 0);
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break;
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case HNS_ROCE_MMAP_TYPE_DWQE:
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ret = rdma_user_mmap_entry_insert_range(
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ucontext, &entry->rdma_entry, length, 1,
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U32_MAX);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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if (ret) {
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kfree(entry);
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return NULL;
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}
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return entry;
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}
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static void hns_roce_dealloc_uar_entry(struct hns_roce_ucontext *context)
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{
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if (context->db_mmap_entry)
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rdma_user_mmap_entry_remove(
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&context->db_mmap_entry->rdma_entry);
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}
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static int hns_roce_alloc_uar_entry(struct ib_ucontext *uctx)
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{
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struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
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u64 address;
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address = context->uar.pfn << PAGE_SHIFT;
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context->db_mmap_entry = hns_roce_user_mmap_entry_insert(
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uctx, address, PAGE_SIZE, HNS_ROCE_MMAP_TYPE_DB);
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if (!context->db_mmap_entry)
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return -ENOMEM;
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return 0;
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}
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static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
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struct ib_udata *udata)
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{
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int ret;
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struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
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struct hns_roce_ib_alloc_ucontext_resp resp = {};
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struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
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if (!hr_dev->active)
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return -EAGAIN;
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resp.qp_tab_size = hr_dev->caps.num_qps;
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resp.srq_tab_size = hr_dev->caps.num_srqs;
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ret = hns_roce_uar_alloc(hr_dev, &context->uar);
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if (ret)
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goto error_fail_uar_alloc;
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ret = hns_roce_alloc_uar_entry(uctx);
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if (ret)
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goto error_fail_uar_entry;
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if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
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hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
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INIT_LIST_HEAD(&context->page_list);
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mutex_init(&context->page_mutex);
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}
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resp.cqe_size = hr_dev->caps.cqe_sz;
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ret = ib_copy_to_udata(udata, &resp,
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min(udata->outlen, sizeof(resp)));
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if (ret)
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goto error_fail_copy_to_udata;
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return 0;
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error_fail_copy_to_udata:
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hns_roce_dealloc_uar_entry(context);
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error_fail_uar_entry:
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ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
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error_fail_uar_alloc:
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return ret;
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}
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static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
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{
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struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
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struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device);
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hns_roce_dealloc_uar_entry(context);
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ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
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}
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|
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static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma)
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{
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struct rdma_user_mmap_entry *rdma_entry;
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struct hns_user_mmap_entry *entry;
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phys_addr_t pfn;
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pgprot_t prot;
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int ret;
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rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma->vm_pgoff);
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if (!rdma_entry)
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return -EINVAL;
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entry = to_hns_mmap(rdma_entry);
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pfn = entry->address >> PAGE_SHIFT;
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|
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switch (entry->mmap_type) {
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case HNS_ROCE_MMAP_TYPE_DB:
|
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case HNS_ROCE_MMAP_TYPE_DWQE:
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prot = pgprot_device(vma->vm_page_prot);
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|
break;
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|
default:
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return -EINVAL;
|
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}
|
|
|
|
ret = rdma_user_mmap_io(uctx, vma, pfn, rdma_entry->npages * PAGE_SIZE,
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prot, rdma_entry);
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|
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rdma_user_mmap_entry_put(rdma_entry);
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|
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return ret;
|
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}
|
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|
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static void hns_roce_free_mmap(struct rdma_user_mmap_entry *rdma_entry)
|
|
{
|
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struct hns_user_mmap_entry *entry = to_hns_mmap(rdma_entry);
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|
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kfree(entry);
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}
|
|
|
|
static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num,
|
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struct ib_port_immutable *immutable)
|
|
{
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struct ib_port_attr attr;
|
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int ret;
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|
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ret = ib_query_port(ib_dev, port_num, &attr);
|
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if (ret)
|
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return ret;
|
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|
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immutable->pkey_tbl_len = attr.pkey_tbl_len;
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immutable->gid_tbl_len = attr.gid_tbl_len;
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|
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immutable->max_mad_size = IB_MGMT_MAD_SIZE;
|
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immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
|
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if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
|
|
immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
|
|
{
|
|
}
|
|
|
|
static void hns_roce_get_fw_ver(struct ib_device *device, char *str)
|
|
{
|
|
u64 fw_ver = to_hr_dev(device)->caps.fw_ver;
|
|
unsigned int major, minor, sub_minor;
|
|
|
|
major = upper_32_bits(fw_ver);
|
|
minor = high_16_bits(lower_32_bits(fw_ver));
|
|
sub_minor = low_16_bits(fw_ver);
|
|
|
|
snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor,
|
|
sub_minor);
|
|
}
|
|
|
|
static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
|
|
{
|
|
struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
|
|
|
|
hr_dev->active = false;
|
|
unregister_netdevice_notifier(&iboe->nb);
|
|
ib_unregister_device(&hr_dev->ib_dev);
|
|
}
|
|
|
|
static const struct ib_device_ops hns_roce_dev_ops = {
|
|
.owner = THIS_MODULE,
|
|
.driver_id = RDMA_DRIVER_HNS,
|
|
.uverbs_abi_ver = 1,
|
|
.uverbs_no_driver_id_binding = 1,
|
|
|
|
.get_dev_fw_str = hns_roce_get_fw_ver,
|
|
.add_gid = hns_roce_add_gid,
|
|
.alloc_pd = hns_roce_alloc_pd,
|
|
.alloc_ucontext = hns_roce_alloc_ucontext,
|
|
.create_ah = hns_roce_create_ah,
|
|
.create_user_ah = hns_roce_create_ah,
|
|
.create_cq = hns_roce_create_cq,
|
|
.create_qp = hns_roce_create_qp,
|
|
.dealloc_pd = hns_roce_dealloc_pd,
|
|
.dealloc_ucontext = hns_roce_dealloc_ucontext,
|
|
.del_gid = hns_roce_del_gid,
|
|
.dereg_mr = hns_roce_dereg_mr,
|
|
.destroy_ah = hns_roce_destroy_ah,
|
|
.destroy_cq = hns_roce_destroy_cq,
|
|
.disassociate_ucontext = hns_roce_disassociate_ucontext,
|
|
.fill_res_cq_entry = hns_roce_fill_res_cq_entry,
|
|
.get_dma_mr = hns_roce_get_dma_mr,
|
|
.get_link_layer = hns_roce_get_link_layer,
|
|
.get_port_immutable = hns_roce_port_immutable,
|
|
.mmap = hns_roce_mmap,
|
|
.mmap_free = hns_roce_free_mmap,
|
|
.modify_device = hns_roce_modify_device,
|
|
.modify_qp = hns_roce_modify_qp,
|
|
.query_ah = hns_roce_query_ah,
|
|
.query_device = hns_roce_query_device,
|
|
.query_pkey = hns_roce_query_pkey,
|
|
.query_port = hns_roce_query_port,
|
|
.reg_user_mr = hns_roce_reg_user_mr,
|
|
|
|
INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
|
|
INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
|
|
INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
|
|
INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp),
|
|
INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
|
|
};
|
|
|
|
static const struct ib_device_ops hns_roce_dev_mr_ops = {
|
|
.rereg_user_mr = hns_roce_rereg_user_mr,
|
|
};
|
|
|
|
static const struct ib_device_ops hns_roce_dev_mw_ops = {
|
|
.alloc_mw = hns_roce_alloc_mw,
|
|
.dealloc_mw = hns_roce_dealloc_mw,
|
|
|
|
INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
|
|
};
|
|
|
|
static const struct ib_device_ops hns_roce_dev_frmr_ops = {
|
|
.alloc_mr = hns_roce_alloc_mr,
|
|
.map_mr_sg = hns_roce_map_mr_sg,
|
|
};
|
|
|
|
static const struct ib_device_ops hns_roce_dev_srq_ops = {
|
|
.create_srq = hns_roce_create_srq,
|
|
.destroy_srq = hns_roce_destroy_srq,
|
|
|
|
INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
|
|
};
|
|
|
|
static const struct ib_device_ops hns_roce_dev_xrcd_ops = {
|
|
.alloc_xrcd = hns_roce_alloc_xrcd,
|
|
.dealloc_xrcd = hns_roce_dealloc_xrcd,
|
|
|
|
INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd),
|
|
};
|
|
|
|
static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
|
|
{
|
|
int ret;
|
|
struct hns_roce_ib_iboe *iboe = NULL;
|
|
struct ib_device *ib_dev = NULL;
|
|
struct device *dev = hr_dev->dev;
|
|
unsigned int i;
|
|
|
|
iboe = &hr_dev->iboe;
|
|
spin_lock_init(&iboe->lock);
|
|
|
|
ib_dev = &hr_dev->ib_dev;
|
|
|
|
ib_dev->node_type = RDMA_NODE_IB_CA;
|
|
ib_dev->dev.parent = dev;
|
|
|
|
ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
|
|
ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
|
|
ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
|
|
|
|
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR)
|
|
ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
|
|
|
|
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW)
|
|
ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
|
|
|
|
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
|
|
ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
|
|
|
|
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
|
|
ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
|
|
ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
|
|
}
|
|
|
|
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
|
|
ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops);
|
|
|
|
ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
|
|
ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
|
|
for (i = 0; i < hr_dev->caps.num_ports; i++) {
|
|
if (!hr_dev->iboe.netdevs[i])
|
|
continue;
|
|
|
|
ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
|
|
i + 1);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
dma_set_max_seg_size(dev, UINT_MAX);
|
|
ret = ib_register_device(ib_dev, "hns_%d", dev);
|
|
if (ret) {
|
|
dev_err(dev, "ib_register_device failed!\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = hns_roce_setup_mtu_mac(hr_dev);
|
|
if (ret) {
|
|
dev_err(dev, "setup_mtu_mac failed!\n");
|
|
goto error_failed_setup_mtu_mac;
|
|
}
|
|
|
|
iboe->nb.notifier_call = hns_roce_netdev_event;
|
|
ret = register_netdevice_notifier(&iboe->nb);
|
|
if (ret) {
|
|
dev_err(dev, "register_netdevice_notifier failed!\n");
|
|
goto error_failed_setup_mtu_mac;
|
|
}
|
|
|
|
hr_dev->active = true;
|
|
return 0;
|
|
|
|
error_failed_setup_mtu_mac:
|
|
ib_unregister_device(ib_dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
|
|
{
|
|
struct device *dev = hr_dev->dev;
|
|
int ret;
|
|
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
|
|
HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
|
|
hr_dev->caps.num_mtpts, 1);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
|
|
HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
|
|
hr_dev->caps.num_qps, 1);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to init QP context memory, aborting.\n");
|
|
goto err_unmap_dmpt;
|
|
}
|
|
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
|
|
HEM_TYPE_IRRL,
|
|
hr_dev->caps.irrl_entry_sz *
|
|
hr_dev->caps.max_qp_init_rdma,
|
|
hr_dev->caps.num_qps, 1);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
|
|
goto err_unmap_qp;
|
|
}
|
|
|
|
if (hr_dev->caps.trrl_entry_sz) {
|
|
ret = hns_roce_init_hem_table(hr_dev,
|
|
&hr_dev->qp_table.trrl_table,
|
|
HEM_TYPE_TRRL,
|
|
hr_dev->caps.trrl_entry_sz *
|
|
hr_dev->caps.max_qp_dest_rdma,
|
|
hr_dev->caps.num_qps, 1);
|
|
if (ret) {
|
|
dev_err(dev,
|
|
"Failed to init trrl_table memory, aborting.\n");
|
|
goto err_unmap_irrl;
|
|
}
|
|
}
|
|
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
|
|
HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
|
|
hr_dev->caps.num_cqs, 1);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to init CQ context memory, aborting.\n");
|
|
goto err_unmap_trrl;
|
|
}
|
|
|
|
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
|
|
HEM_TYPE_SRQC,
|
|
hr_dev->caps.srqc_entry_sz,
|
|
hr_dev->caps.num_srqs, 1);
|
|
if (ret) {
|
|
dev_err(dev,
|
|
"Failed to init SRQ context memory, aborting.\n");
|
|
goto err_unmap_cq;
|
|
}
|
|
}
|
|
|
|
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
|
|
ret = hns_roce_init_hem_table(hr_dev,
|
|
&hr_dev->qp_table.sccc_table,
|
|
HEM_TYPE_SCCC,
|
|
hr_dev->caps.sccc_sz,
|
|
hr_dev->caps.num_qps, 1);
|
|
if (ret) {
|
|
dev_err(dev,
|
|
"Failed to init SCC context memory, aborting.\n");
|
|
goto err_unmap_srq;
|
|
}
|
|
}
|
|
|
|
if (hr_dev->caps.qpc_timer_entry_sz) {
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
|
|
HEM_TYPE_QPC_TIMER,
|
|
hr_dev->caps.qpc_timer_entry_sz,
|
|
hr_dev->caps.num_qpc_timer, 1);
|
|
if (ret) {
|
|
dev_err(dev,
|
|
"Failed to init QPC timer memory, aborting.\n");
|
|
goto err_unmap_ctx;
|
|
}
|
|
}
|
|
|
|
if (hr_dev->caps.cqc_timer_entry_sz) {
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
|
|
HEM_TYPE_CQC_TIMER,
|
|
hr_dev->caps.cqc_timer_entry_sz,
|
|
hr_dev->caps.num_cqc_timer, 1);
|
|
if (ret) {
|
|
dev_err(dev,
|
|
"Failed to init CQC timer memory, aborting.\n");
|
|
goto err_unmap_qpc_timer;
|
|
}
|
|
}
|
|
|
|
if (hr_dev->caps.gmv_entry_sz) {
|
|
ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table,
|
|
HEM_TYPE_GMV,
|
|
hr_dev->caps.gmv_entry_sz,
|
|
hr_dev->caps.gmv_entry_num, 1);
|
|
if (ret) {
|
|
dev_err(dev,
|
|
"failed to init gmv table memory, ret = %d\n",
|
|
ret);
|
|
goto err_unmap_cqc_timer;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_unmap_cqc_timer:
|
|
if (hr_dev->caps.cqc_timer_entry_sz)
|
|
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table);
|
|
|
|
err_unmap_qpc_timer:
|
|
if (hr_dev->caps.qpc_timer_entry_sz)
|
|
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
|
|
|
|
err_unmap_ctx:
|
|
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
|
|
hns_roce_cleanup_hem_table(hr_dev,
|
|
&hr_dev->qp_table.sccc_table);
|
|
err_unmap_srq:
|
|
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
|
|
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
|
|
|
|
err_unmap_cq:
|
|
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
|
|
|
|
err_unmap_trrl:
|
|
if (hr_dev->caps.trrl_entry_sz)
|
|
hns_roce_cleanup_hem_table(hr_dev,
|
|
&hr_dev->qp_table.trrl_table);
|
|
|
|
err_unmap_irrl:
|
|
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
|
|
|
|
err_unmap_qp:
|
|
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
|
|
|
|
err_unmap_dmpt:
|
|
hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* hns_roce_setup_hca - setup host channel adapter
|
|
* @hr_dev: pointer to hns roce device
|
|
* Return : int
|
|
*/
|
|
static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
|
|
{
|
|
struct device *dev = hr_dev->dev;
|
|
int ret;
|
|
|
|
spin_lock_init(&hr_dev->sm_lock);
|
|
|
|
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
|
|
hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
|
|
INIT_LIST_HEAD(&hr_dev->pgdir_list);
|
|
mutex_init(&hr_dev->pgdir_mutex);
|
|
}
|
|
|
|
hns_roce_init_uar_table(hr_dev);
|
|
|
|
ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to allocate priv_uar.\n");
|
|
goto err_uar_table_free;
|
|
}
|
|
|
|
ret = hns_roce_init_qp_table(hr_dev);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to init qp_table.\n");
|
|
goto err_uar_table_free;
|
|
}
|
|
|
|
hns_roce_init_pd_table(hr_dev);
|
|
|
|
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
|
|
hns_roce_init_xrcd_table(hr_dev);
|
|
|
|
hns_roce_init_mr_table(hr_dev);
|
|
|
|
hns_roce_init_cq_table(hr_dev);
|
|
|
|
if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
|
|
hns_roce_init_srq_table(hr_dev);
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_uar_table_free:
|
|
ida_destroy(&hr_dev->uar_ida.ida);
|
|
return ret;
|
|
}
|
|
|
|
static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
|
|
{
|
|
struct hns_roce_cq *hr_cq = to_hr_cq(cq);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&hr_cq->lock, flags);
|
|
if (cq->comp_handler) {
|
|
if (!hr_cq->is_armed) {
|
|
hr_cq->is_armed = 1;
|
|
list_add_tail(&hr_cq->node, cq_list);
|
|
}
|
|
}
|
|
spin_unlock_irqrestore(&hr_cq->lock, flags);
|
|
}
|
|
|
|
void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
|
|
{
|
|
struct hns_roce_qp *hr_qp;
|
|
struct hns_roce_cq *hr_cq;
|
|
struct list_head cq_list;
|
|
unsigned long flags_qp;
|
|
unsigned long flags;
|
|
|
|
INIT_LIST_HEAD(&cq_list);
|
|
|
|
spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
|
|
list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
|
|
spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
|
|
if (hr_qp->sq.tail != hr_qp->sq.head)
|
|
check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
|
|
spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
|
|
|
|
spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
|
|
if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
|
|
check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
|
|
spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
|
|
}
|
|
|
|
list_for_each_entry(hr_cq, &cq_list, node)
|
|
hns_roce_cq_completion(hr_dev, hr_cq->cqn);
|
|
|
|
spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
|
|
}
|
|
|
|
int hns_roce_init(struct hns_roce_dev *hr_dev)
|
|
{
|
|
struct device *dev = hr_dev->dev;
|
|
int ret;
|
|
|
|
hr_dev->is_reset = false;
|
|
|
|
if (hr_dev->hw->cmq_init) {
|
|
ret = hr_dev->hw->cmq_init(hr_dev);
|
|
if (ret) {
|
|
dev_err(dev, "Init RoCE Command Queue failed!\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
ret = hr_dev->hw->hw_profile(hr_dev);
|
|
if (ret) {
|
|
dev_err(dev, "Get RoCE engine profile failed!\n");
|
|
goto error_failed_cmd_init;
|
|
}
|
|
|
|
ret = hns_roce_cmd_init(hr_dev);
|
|
if (ret) {
|
|
dev_err(dev, "cmd init failed!\n");
|
|
goto error_failed_cmd_init;
|
|
}
|
|
|
|
/* EQ depends on poll mode, event mode depends on EQ */
|
|
ret = hr_dev->hw->init_eq(hr_dev);
|
|
if (ret) {
|
|
dev_err(dev, "eq init failed!\n");
|
|
goto error_failed_eq_table;
|
|
}
|
|
|
|
if (hr_dev->cmd_mod) {
|
|
ret = hns_roce_cmd_use_events(hr_dev);
|
|
if (ret)
|
|
dev_warn(dev,
|
|
"Cmd event mode failed, set back to poll!\n");
|
|
}
|
|
|
|
ret = hns_roce_init_hem(hr_dev);
|
|
if (ret) {
|
|
dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
|
|
goto error_failed_init_hem;
|
|
}
|
|
|
|
ret = hns_roce_setup_hca(hr_dev);
|
|
if (ret) {
|
|
dev_err(dev, "setup hca failed!\n");
|
|
goto error_failed_setup_hca;
|
|
}
|
|
|
|
if (hr_dev->hw->hw_init) {
|
|
ret = hr_dev->hw->hw_init(hr_dev);
|
|
if (ret) {
|
|
dev_err(dev, "hw_init failed!\n");
|
|
goto error_failed_engine_init;
|
|
}
|
|
}
|
|
|
|
INIT_LIST_HEAD(&hr_dev->qp_list);
|
|
spin_lock_init(&hr_dev->qp_list_lock);
|
|
INIT_LIST_HEAD(&hr_dev->dip_list);
|
|
spin_lock_init(&hr_dev->dip_list_lock);
|
|
|
|
ret = hns_roce_register_device(hr_dev);
|
|
if (ret)
|
|
goto error_failed_register_device;
|
|
|
|
return 0;
|
|
|
|
error_failed_register_device:
|
|
if (hr_dev->hw->hw_exit)
|
|
hr_dev->hw->hw_exit(hr_dev);
|
|
|
|
error_failed_engine_init:
|
|
hns_roce_cleanup_bitmap(hr_dev);
|
|
|
|
error_failed_setup_hca:
|
|
hns_roce_cleanup_hem(hr_dev);
|
|
|
|
error_failed_init_hem:
|
|
if (hr_dev->cmd_mod)
|
|
hns_roce_cmd_use_polling(hr_dev);
|
|
hr_dev->hw->cleanup_eq(hr_dev);
|
|
|
|
error_failed_eq_table:
|
|
hns_roce_cmd_cleanup(hr_dev);
|
|
|
|
error_failed_cmd_init:
|
|
if (hr_dev->hw->cmq_exit)
|
|
hr_dev->hw->cmq_exit(hr_dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void hns_roce_exit(struct hns_roce_dev *hr_dev)
|
|
{
|
|
hns_roce_unregister_device(hr_dev);
|
|
|
|
if (hr_dev->hw->hw_exit)
|
|
hr_dev->hw->hw_exit(hr_dev);
|
|
hns_roce_cleanup_bitmap(hr_dev);
|
|
hns_roce_cleanup_hem(hr_dev);
|
|
|
|
if (hr_dev->cmd_mod)
|
|
hns_roce_cmd_use_polling(hr_dev);
|
|
|
|
hr_dev->hw->cleanup_eq(hr_dev);
|
|
hns_roce_cmd_cleanup(hr_dev);
|
|
if (hr_dev->hw->cmq_exit)
|
|
hr_dev->hw->cmq_exit(hr_dev);
|
|
}
|
|
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
|
MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
|
|
MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
|
|
MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
|
|
MODULE_DESCRIPTION("HNS RoCE Driver");
|