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75b6f6487c
Intel NTB device has custom LTR management that is not compliant with the PCIe standard. Add support to set LTR status triggered by link status change. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
185 lines
7.7 KiB
C
185 lines
7.7 KiB
C
/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copy
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _NTB_INTEL_GEN1_H_
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#define _NTB_INTEL_GEN1_H_
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#include "ntb_hw_intel.h"
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/* Intel Gen1 Xeon hardware */
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#define XEON_PBAR23LMT_OFFSET 0x0000
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#define XEON_PBAR45LMT_OFFSET 0x0008
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#define XEON_PBAR4LMT_OFFSET 0x0008
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#define XEON_PBAR5LMT_OFFSET 0x000c
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#define XEON_PBAR23XLAT_OFFSET 0x0010
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#define XEON_PBAR45XLAT_OFFSET 0x0018
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#define XEON_PBAR4XLAT_OFFSET 0x0018
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#define XEON_PBAR5XLAT_OFFSET 0x001c
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#define XEON_SBAR23LMT_OFFSET 0x0020
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#define XEON_SBAR45LMT_OFFSET 0x0028
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#define XEON_SBAR4LMT_OFFSET 0x0028
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#define XEON_SBAR5LMT_OFFSET 0x002c
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#define XEON_SBAR23XLAT_OFFSET 0x0030
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#define XEON_SBAR45XLAT_OFFSET 0x0038
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#define XEON_SBAR4XLAT_OFFSET 0x0038
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#define XEON_SBAR5XLAT_OFFSET 0x003c
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#define XEON_SBAR0BASE_OFFSET 0x0040
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#define XEON_SBAR23BASE_OFFSET 0x0048
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#define XEON_SBAR45BASE_OFFSET 0x0050
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#define XEON_SBAR4BASE_OFFSET 0x0050
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#define XEON_SBAR5BASE_OFFSET 0x0054
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#define XEON_SBDF_OFFSET 0x005c
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#define XEON_NTBCNTL_OFFSET 0x0058
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#define XEON_PDOORBELL_OFFSET 0x0060
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#define XEON_PDBMSK_OFFSET 0x0062
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#define XEON_SDOORBELL_OFFSET 0x0064
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#define XEON_SDBMSK_OFFSET 0x0066
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#define XEON_USMEMMISS_OFFSET 0x0070
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#define XEON_SPAD_OFFSET 0x0080
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#define XEON_PBAR23SZ_OFFSET 0x00d0
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#define XEON_PBAR45SZ_OFFSET 0x00d1
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#define XEON_PBAR4SZ_OFFSET 0x00d1
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#define XEON_SBAR23SZ_OFFSET 0x00d2
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#define XEON_SBAR45SZ_OFFSET 0x00d3
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#define XEON_SBAR4SZ_OFFSET 0x00d3
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#define XEON_PPD_OFFSET 0x00d4
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#define XEON_PBAR5SZ_OFFSET 0x00d5
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#define XEON_SBAR5SZ_OFFSET 0x00d6
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#define XEON_WCCNTRL_OFFSET 0x00e0
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#define XEON_UNCERRSTS_OFFSET 0x014c
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#define XEON_CORERRSTS_OFFSET 0x0158
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#define XEON_LINK_STATUS_OFFSET 0x01a2
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#define XEON_SPCICMD_OFFSET 0x0504
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#define XEON_DEVCTRL_OFFSET 0x0598
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#define XEON_DEVSTS_OFFSET 0x059a
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#define XEON_SLINK_STATUS_OFFSET 0x05a2
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#define XEON_B2B_SPAD_OFFSET 0x0100
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#define XEON_B2B_DOORBELL_OFFSET 0x0140
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#define XEON_B2B_XLAT_OFFSETL 0x0144
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#define XEON_B2B_XLAT_OFFSETU 0x0148
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#define XEON_PPD_CONN_MASK 0x03
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#define XEON_PPD_CONN_TRANSPARENT 0x00
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#define XEON_PPD_CONN_B2B 0x01
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#define XEON_PPD_CONN_RP 0x02
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#define XEON_PPD_DEV_MASK 0x10
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#define XEON_PPD_DEV_USD 0x00
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#define XEON_PPD_DEV_DSD 0x10
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#define XEON_PPD_SPLIT_BAR_MASK 0x40
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#define XEON_PPD_TOPO_MASK (XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK)
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#define XEON_PPD_TOPO_PRI_USD (XEON_PPD_CONN_RP | XEON_PPD_DEV_USD)
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#define XEON_PPD_TOPO_PRI_DSD (XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD)
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#define XEON_PPD_TOPO_SEC_USD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD)
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#define XEON_PPD_TOPO_SEC_DSD (XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD)
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#define XEON_PPD_TOPO_B2B_USD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD)
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#define XEON_PPD_TOPO_B2B_DSD (XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD)
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#define XEON_MW_COUNT 2
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#define HSX_SPLIT_BAR_MW_COUNT 3
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#define XEON_DB_COUNT 15
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#define XEON_DB_LINK 15
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#define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK)
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#define XEON_DB_MSIX_VECTOR_COUNT 4
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#define XEON_DB_MSIX_VECTOR_SHIFT 5
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#define XEON_DB_TOTAL_SHIFT 16
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#define XEON_SPAD_COUNT 16
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/* Use the following addresses for translation between b2b ntb devices in case
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* the hardware default values are not reliable. */
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#define XEON_B2B_BAR0_ADDR 0x1000000000000000ull
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#define XEON_B2B_BAR2_ADDR64 0x2000000000000000ull
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#define XEON_B2B_BAR4_ADDR64 0x4000000000000000ull
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#define XEON_B2B_BAR4_ADDR32 0x20000000u
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#define XEON_B2B_BAR5_ADDR32 0x40000000u
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/* The peer ntb secondary config space is 32KB fixed size */
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#define XEON_B2B_MIN_SIZE 0x8000
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/* flags to indicate hardware errata */
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#define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0)
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#define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1)
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#define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2)
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#define NTB_HWERR_MSIX_VECTOR32_BAD BIT_ULL(3)
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#define NTB_HWERR_BAR_ALIGN BIT_ULL(4)
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#define NTB_HWERR_LTR_BAD BIT_ULL(5)
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extern struct intel_b2b_addr xeon_b2b_usd_addr;
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extern struct intel_b2b_addr xeon_b2b_dsd_addr;
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int ndev_init_isr(struct intel_ntb_dev *ndev, int msix_min, int msix_max,
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int msix_shift, int total_shift);
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enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd);
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void ndev_db_addr(struct intel_ntb_dev *ndev,
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phys_addr_t *db_addr, resource_size_t *db_size,
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phys_addr_t reg_addr, unsigned long reg);
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u64 ndev_db_read(struct intel_ntb_dev *ndev, void __iomem *mmio);
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int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits,
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void __iomem *mmio);
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int ndev_mw_to_bar(struct intel_ntb_dev *ndev, int idx);
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int intel_ntb_mw_count(struct ntb_dev *ntb, int pidx);
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int intel_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int idx,
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resource_size_t *addr_align, resource_size_t *size_align,
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resource_size_t *size_max);
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int intel_ntb_peer_mw_count(struct ntb_dev *ntb);
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int intel_ntb_peer_mw_get_addr(struct ntb_dev *ntb, int idx,
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phys_addr_t *base, resource_size_t *size);
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u64 intel_ntb_link_is_up(struct ntb_dev *ntb, enum ntb_speed *speed,
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enum ntb_width *width);
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int intel_ntb_link_disable(struct ntb_dev *ntb);
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u64 intel_ntb_db_valid_mask(struct ntb_dev *ntb);
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int intel_ntb_db_vector_count(struct ntb_dev *ntb);
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u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector);
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int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits);
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int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits);
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int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb);
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int intel_ntb_spad_count(struct ntb_dev *ntb);
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u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx);
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int intel_ntb_spad_write(struct ntb_dev *ntb, int idx, u32 val);
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u32 intel_ntb_peer_spad_read(struct ntb_dev *ntb, int pidx, int sidx);
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int intel_ntb_peer_spad_write(struct ntb_dev *ntb, int pidx, int sidx,
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u32 val);
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int intel_ntb_peer_spad_addr(struct ntb_dev *ntb, int pidx, int sidx,
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phys_addr_t *spad_addr);
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int xeon_link_is_up(struct intel_ntb_dev *ndev);
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#endif
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