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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
177 lines
4.8 KiB
C
177 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Fault injection for both 32 and 64bit guests.
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*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Based on arch/arm/kvm/emulate.c
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#include <asm/esr.h>
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#define PSTATE_FAULT_BITS_64 (PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | \
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PSR_I_BIT | PSR_D_BIT)
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#define CURRENT_EL_SP_EL0_VECTOR 0x0
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#define CURRENT_EL_SP_ELx_VECTOR 0x200
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#define LOWER_EL_AArch64_VECTOR 0x400
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#define LOWER_EL_AArch32_VECTOR 0x600
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enum exception_type {
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except_type_sync = 0,
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except_type_irq = 0x80,
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except_type_fiq = 0x100,
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except_type_serror = 0x180,
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};
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static u64 get_except_vector(struct kvm_vcpu *vcpu, enum exception_type type)
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{
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u64 exc_offset;
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switch (*vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT)) {
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case PSR_MODE_EL1t:
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exc_offset = CURRENT_EL_SP_EL0_VECTOR;
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break;
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case PSR_MODE_EL1h:
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exc_offset = CURRENT_EL_SP_ELx_VECTOR;
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break;
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case PSR_MODE_EL0t:
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exc_offset = LOWER_EL_AArch64_VECTOR;
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break;
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default:
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exc_offset = LOWER_EL_AArch32_VECTOR;
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}
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return vcpu_read_sys_reg(vcpu, VBAR_EL1) + exc_offset + type;
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}
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static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
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{
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unsigned long cpsr = *vcpu_cpsr(vcpu);
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bool is_aarch32 = vcpu_mode_is_32bit(vcpu);
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u32 esr = 0;
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vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
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*vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
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*vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
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vcpu_write_spsr(vcpu, cpsr);
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vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
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/*
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* Build an {i,d}abort, depending on the level and the
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* instruction set. Report an external synchronous abort.
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*/
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if (kvm_vcpu_trap_il_is32bit(vcpu))
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esr |= ESR_ELx_IL;
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/*
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* Here, the guest runs in AArch64 mode when in EL1. If we get
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* an AArch32 fault, it means we managed to trap an EL0 fault.
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*/
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if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t)
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esr |= (ESR_ELx_EC_IABT_LOW << ESR_ELx_EC_SHIFT);
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else
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esr |= (ESR_ELx_EC_IABT_CUR << ESR_ELx_EC_SHIFT);
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if (!is_iabt)
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esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT;
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vcpu_write_sys_reg(vcpu, esr | ESR_ELx_FSC_EXTABT, ESR_EL1);
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}
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static void inject_undef64(struct kvm_vcpu *vcpu)
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{
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unsigned long cpsr = *vcpu_cpsr(vcpu);
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u32 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
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vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
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*vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
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*vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
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vcpu_write_spsr(vcpu, cpsr);
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/*
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* Build an unknown exception, depending on the instruction
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* set.
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*/
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if (kvm_vcpu_trap_il_is32bit(vcpu))
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esr |= ESR_ELx_IL;
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vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
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}
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/**
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* kvm_inject_dabt - inject a data abort into the guest
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* @vcpu: The VCPU to receive the undefined exception
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* @addr: The address to report in the DFAR
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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if (vcpu_el1_is_32bit(vcpu))
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kvm_inject_dabt32(vcpu, addr);
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else
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inject_abt64(vcpu, false, addr);
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}
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/**
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* kvm_inject_pabt - inject a prefetch abort into the guest
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* @vcpu: The VCPU to receive the undefined exception
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* @addr: The address to report in the DFAR
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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if (vcpu_el1_is_32bit(vcpu))
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kvm_inject_pabt32(vcpu, addr);
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else
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inject_abt64(vcpu, true, addr);
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}
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/**
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* kvm_inject_undefined - inject an undefined instruction into the guest
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_undefined(struct kvm_vcpu *vcpu)
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{
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if (vcpu_el1_is_32bit(vcpu))
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kvm_inject_undef32(vcpu);
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else
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inject_undef64(vcpu);
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}
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void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 esr)
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{
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vcpu_set_vsesr(vcpu, esr & ESR_ELx_ISS_MASK);
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*vcpu_hcr(vcpu) |= HCR_VSE;
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}
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/**
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* kvm_inject_vabt - inject an async abort / SError into the guest
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* @vcpu: The VCPU to receive the exception
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*
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* Systems with the RAS Extensions specify an imp-def ESR (ISV/IDS = 1) with
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* the remaining ISS all-zeros so that this error is not interpreted as an
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* uncategorized RAS error. Without the RAS Extensions we can't specify an ESR
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* value, so the CPU generates an imp-def value.
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*/
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void kvm_inject_vabt(struct kvm_vcpu *vcpu)
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{
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kvm_set_sei_esr(vcpu, ESR_ELx_ISV);
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}
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