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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 655 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
56 lines
2 KiB
C
56 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Flora Fu, MediaTek
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135
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#define _DT_BINDINGS_RESET_CONTROLLER_MT8135
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/* INFRACFG resets */
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#define MT8135_INFRA_EMI_REG_RST 0
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#define MT8135_INFRA_DRAMC0_A0_RST 1
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#define MT8135_INFRA_CCIF0_RST 2
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#define MT8135_INFRA_APCIRQ_EINT_RST 3
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#define MT8135_INFRA_APXGPT_RST 4
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#define MT8135_INFRA_SCPSYS_RST 5
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#define MT8135_INFRA_CCIF1_RST 6
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#define MT8135_INFRA_PMIC_WRAP_RST 7
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#define MT8135_INFRA_KP_RST 8
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#define MT8135_INFRA_EMI_RST 32
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#define MT8135_INFRA_DRAMC0_RST 34
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#define MT8135_INFRA_SMI_RST 35
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#define MT8135_INFRA_M4U_RST 36
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/* PERICFG resets */
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#define MT8135_PERI_UART0_SW_RST 0
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#define MT8135_PERI_UART1_SW_RST 1
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#define MT8135_PERI_UART2_SW_RST 2
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#define MT8135_PERI_UART3_SW_RST 3
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#define MT8135_PERI_IRDA_SW_RST 4
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#define MT8135_PERI_PTP_SW_RST 5
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#define MT8135_PERI_AP_HIF_SW_RST 6
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#define MT8135_PERI_GPCU_SW_RST 7
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#define MT8135_PERI_MD_HIF_SW_RST 8
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#define MT8135_PERI_NLI_SW_RST 9
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#define MT8135_PERI_AUXADC_SW_RST 10
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#define MT8135_PERI_DMA_SW_RST 11
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#define MT8135_PERI_NFI_SW_RST 14
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#define MT8135_PERI_PWM_SW_RST 15
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#define MT8135_PERI_THERM_SW_RST 16
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#define MT8135_PERI_MSDC0_SW_RST 17
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#define MT8135_PERI_MSDC1_SW_RST 18
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#define MT8135_PERI_MSDC2_SW_RST 19
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#define MT8135_PERI_MSDC3_SW_RST 20
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#define MT8135_PERI_I2C0_SW_RST 22
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#define MT8135_PERI_I2C1_SW_RST 23
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#define MT8135_PERI_I2C2_SW_RST 24
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#define MT8135_PERI_I2C3_SW_RST 25
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#define MT8135_PERI_I2C4_SW_RST 26
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#define MT8135_PERI_I2C5_SW_RST 27
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#define MT8135_PERI_I2C6_SW_RST 28
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#define MT8135_PERI_USB_SW_RST 29
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#define MT8135_PERI_SPI1_SW_RST 33
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#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */
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