mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 17:30:02 +00:00
![Dave Gordon](/assets/img/avatar_default.png)
The existing for_each_sg_page() iterator is somewhat heavyweight, and is limiting i915 driver performance in a few benchmarks. So here we introduce somewhat lighter weight iterators, primarily for use with GEM objects or other case where we need only deal with whole aligned pages. Unlike the old iterator, the new iterators use an internal state structure which is not intended to be accessed by the caller; instead each takes as a parameter an output variable which is set before each iteration. This makes them particularly simple to use :) One of the new iterators provides the caller with the DMA address of each page in turn; the other provides the 'struct page' pointer required by many memory management operations. Various uses of for_each_sg_page() are then converted to the new macros. v2: Force inlining of the sg_iter constructor and make the union anonymous. Signed-off-by: Dave Gordon <david.s.gordon@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: http://patchwork.freedesktop.org/patch/msgid/1463741647-15666-4-git-send-email-chris@chris-wilson.co.uk
802 lines
25 KiB
C
802 lines
25 KiB
C
/*
|
|
* Copyright © 2008-2015 Intel Corporation
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice (including the next
|
|
* paragraph) shall be included in all copies or substantial portions of the
|
|
* Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
|
* IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include <drm/drmP.h>
|
|
#include <drm/i915_drm.h>
|
|
#include "i915_drv.h"
|
|
|
|
/**
|
|
* DOC: fence register handling
|
|
*
|
|
* Important to avoid confusions: "fences" in the i915 driver are not execution
|
|
* fences used to track command completion but hardware detiler objects which
|
|
* wrap a given range of the global GTT. Each platform has only a fairly limited
|
|
* set of these objects.
|
|
*
|
|
* Fences are used to detile GTT memory mappings. They're also connected to the
|
|
* hardware frontbuffer render tracking and hence interact with frontbuffer
|
|
* compression. Furthermore on older platforms fences are required for tiled
|
|
* objects used by the display engine. They can also be used by the render
|
|
* engine - they're required for blitter commands and are optional for render
|
|
* commands. But on gen4+ both display (with the exception of fbc) and rendering
|
|
* have their own tiling state bits and don't need fences.
|
|
*
|
|
* Also note that fences only support X and Y tiling and hence can't be used for
|
|
* the fancier new tiling formats like W, Ys and Yf.
|
|
*
|
|
* Finally note that because fences are such a restricted resource they're
|
|
* dynamically associated with objects. Furthermore fence state is committed to
|
|
* the hardware lazily to avoid unnecessary stalls on gen2/3. Therefore code must
|
|
* explicitly call i915_gem_object_get_fence() to synchronize fencing status
|
|
* for cpu access. Also note that some code wants an unfenced view, for those
|
|
* cases the fence can be removed forcefully with i915_gem_object_put_fence().
|
|
*
|
|
* Internally these functions will synchronize with userspace access by removing
|
|
* CPU ptes into GTT mmaps (not the GTT ptes themselves) as needed.
|
|
*/
|
|
|
|
static void i965_write_fence_reg(struct drm_device *dev, int reg,
|
|
struct drm_i915_gem_object *obj)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
i915_reg_t fence_reg_lo, fence_reg_hi;
|
|
int fence_pitch_shift;
|
|
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
|
fence_reg_lo = FENCE_REG_GEN6_LO(reg);
|
|
fence_reg_hi = FENCE_REG_GEN6_HI(reg);
|
|
fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT;
|
|
} else {
|
|
fence_reg_lo = FENCE_REG_965_LO(reg);
|
|
fence_reg_hi = FENCE_REG_965_HI(reg);
|
|
fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
|
|
}
|
|
|
|
/* To w/a incoherency with non-atomic 64-bit register updates,
|
|
* we split the 64-bit update into two 32-bit writes. In order
|
|
* for a partial fence not to be evaluated between writes, we
|
|
* precede the update with write to turn off the fence register,
|
|
* and only enable the fence as the last step.
|
|
*
|
|
* For extra levels of paranoia, we make sure each step lands
|
|
* before applying the next step.
|
|
*/
|
|
I915_WRITE(fence_reg_lo, 0);
|
|
POSTING_READ(fence_reg_lo);
|
|
|
|
if (obj) {
|
|
u32 size = i915_gem_obj_ggtt_size(obj);
|
|
uint64_t val;
|
|
|
|
/* Adjust fence size to match tiled area */
|
|
if (obj->tiling_mode != I915_TILING_NONE) {
|
|
uint32_t row_size = obj->stride *
|
|
(obj->tiling_mode == I915_TILING_Y ? 32 : 8);
|
|
size = (size / row_size) * row_size;
|
|
}
|
|
|
|
val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
|
|
0xfffff000) << 32;
|
|
val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
|
|
val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
|
|
if (obj->tiling_mode == I915_TILING_Y)
|
|
val |= 1 << I965_FENCE_TILING_Y_SHIFT;
|
|
val |= I965_FENCE_REG_VALID;
|
|
|
|
I915_WRITE(fence_reg_hi, val >> 32);
|
|
POSTING_READ(fence_reg_hi);
|
|
|
|
I915_WRITE(fence_reg_lo, val);
|
|
POSTING_READ(fence_reg_lo);
|
|
} else {
|
|
I915_WRITE(fence_reg_hi, 0);
|
|
POSTING_READ(fence_reg_hi);
|
|
}
|
|
}
|
|
|
|
static void i915_write_fence_reg(struct drm_device *dev, int reg,
|
|
struct drm_i915_gem_object *obj)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
u32 val;
|
|
|
|
if (obj) {
|
|
u32 size = i915_gem_obj_ggtt_size(obj);
|
|
int pitch_val;
|
|
int tile_width;
|
|
|
|
WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
|
|
(size & -size) != size ||
|
|
(i915_gem_obj_ggtt_offset(obj) & (size - 1)),
|
|
"object 0x%08llx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
|
|
i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
|
|
|
|
if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
|
|
tile_width = 128;
|
|
else
|
|
tile_width = 512;
|
|
|
|
/* Note: pitch better be a power of two tile widths */
|
|
pitch_val = obj->stride / tile_width;
|
|
pitch_val = ffs(pitch_val) - 1;
|
|
|
|
val = i915_gem_obj_ggtt_offset(obj);
|
|
if (obj->tiling_mode == I915_TILING_Y)
|
|
val |= 1 << I830_FENCE_TILING_Y_SHIFT;
|
|
val |= I915_FENCE_SIZE_BITS(size);
|
|
val |= pitch_val << I830_FENCE_PITCH_SHIFT;
|
|
val |= I830_FENCE_REG_VALID;
|
|
} else
|
|
val = 0;
|
|
|
|
I915_WRITE(FENCE_REG(reg), val);
|
|
POSTING_READ(FENCE_REG(reg));
|
|
}
|
|
|
|
static void i830_write_fence_reg(struct drm_device *dev, int reg,
|
|
struct drm_i915_gem_object *obj)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
uint32_t val;
|
|
|
|
if (obj) {
|
|
u32 size = i915_gem_obj_ggtt_size(obj);
|
|
uint32_t pitch_val;
|
|
|
|
WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
|
|
(size & -size) != size ||
|
|
(i915_gem_obj_ggtt_offset(obj) & (size - 1)),
|
|
"object 0x%08llx not 512K or pot-size 0x%08x aligned\n",
|
|
i915_gem_obj_ggtt_offset(obj), size);
|
|
|
|
pitch_val = obj->stride / 128;
|
|
pitch_val = ffs(pitch_val) - 1;
|
|
|
|
val = i915_gem_obj_ggtt_offset(obj);
|
|
if (obj->tiling_mode == I915_TILING_Y)
|
|
val |= 1 << I830_FENCE_TILING_Y_SHIFT;
|
|
val |= I830_FENCE_SIZE_BITS(size);
|
|
val |= pitch_val << I830_FENCE_PITCH_SHIFT;
|
|
val |= I830_FENCE_REG_VALID;
|
|
} else
|
|
val = 0;
|
|
|
|
I915_WRITE(FENCE_REG(reg), val);
|
|
POSTING_READ(FENCE_REG(reg));
|
|
}
|
|
|
|
inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
|
|
{
|
|
return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
|
|
}
|
|
|
|
static void i915_gem_write_fence(struct drm_device *dev, int reg,
|
|
struct drm_i915_gem_object *obj)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
/* Ensure that all CPU reads are completed before installing a fence
|
|
* and all writes before removing the fence.
|
|
*/
|
|
if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
|
|
mb();
|
|
|
|
WARN(obj && (!obj->stride || !obj->tiling_mode),
|
|
"bogus fence setup with stride: 0x%x, tiling mode: %i\n",
|
|
obj->stride, obj->tiling_mode);
|
|
|
|
if (IS_GEN2(dev))
|
|
i830_write_fence_reg(dev, reg, obj);
|
|
else if (IS_GEN3(dev))
|
|
i915_write_fence_reg(dev, reg, obj);
|
|
else if (INTEL_INFO(dev)->gen >= 4)
|
|
i965_write_fence_reg(dev, reg, obj);
|
|
|
|
/* And similarly be paranoid that no direct access to this region
|
|
* is reordered to before the fence is installed.
|
|
*/
|
|
if (i915_gem_object_needs_mb(obj))
|
|
mb();
|
|
}
|
|
|
|
static inline int fence_number(struct drm_i915_private *dev_priv,
|
|
struct drm_i915_fence_reg *fence)
|
|
{
|
|
return fence - dev_priv->fence_regs;
|
|
}
|
|
|
|
static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
|
|
struct drm_i915_fence_reg *fence,
|
|
bool enable)
|
|
{
|
|
struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
|
|
int reg = fence_number(dev_priv, fence);
|
|
|
|
i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
|
|
|
|
if (enable) {
|
|
obj->fence_reg = reg;
|
|
fence->obj = obj;
|
|
list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
|
|
} else {
|
|
obj->fence_reg = I915_FENCE_REG_NONE;
|
|
fence->obj = NULL;
|
|
list_del_init(&fence->lru_list);
|
|
}
|
|
obj->fence_dirty = false;
|
|
}
|
|
|
|
static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
|
|
{
|
|
if (obj->tiling_mode)
|
|
i915_gem_release_mmap(obj);
|
|
|
|
/* As we do not have an associated fence register, we will force
|
|
* a tiling change if we ever need to acquire one.
|
|
*/
|
|
obj->fence_dirty = false;
|
|
obj->fence_reg = I915_FENCE_REG_NONE;
|
|
}
|
|
|
|
static int
|
|
i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
|
|
{
|
|
if (obj->last_fenced_req) {
|
|
int ret = i915_wait_request(obj->last_fenced_req);
|
|
if (ret)
|
|
return ret;
|
|
|
|
i915_gem_request_assign(&obj->last_fenced_req, NULL);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* i915_gem_object_put_fence - force-remove fence for an object
|
|
* @obj: object to map through a fence reg
|
|
*
|
|
* This function force-removes any fence from the given object, which is useful
|
|
* if the kernel wants to do untiled GTT access.
|
|
*
|
|
* Returns:
|
|
*
|
|
* 0 on success, negative error code on failure.
|
|
*/
|
|
int
|
|
i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
|
|
{
|
|
struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
|
|
struct drm_i915_fence_reg *fence;
|
|
int ret;
|
|
|
|
ret = i915_gem_object_wait_fence(obj);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (obj->fence_reg == I915_FENCE_REG_NONE)
|
|
return 0;
|
|
|
|
fence = &dev_priv->fence_regs[obj->fence_reg];
|
|
|
|
if (WARN_ON(fence->pin_count))
|
|
return -EBUSY;
|
|
|
|
i915_gem_object_fence_lost(obj);
|
|
i915_gem_object_update_fence(obj, fence, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct drm_i915_fence_reg *
|
|
i915_find_fence_reg(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct drm_i915_fence_reg *reg, *avail;
|
|
int i;
|
|
|
|
/* First try to find a free reg */
|
|
avail = NULL;
|
|
for (i = 0; i < dev_priv->num_fence_regs; i++) {
|
|
reg = &dev_priv->fence_regs[i];
|
|
if (!reg->obj)
|
|
return reg;
|
|
|
|
if (!reg->pin_count)
|
|
avail = reg;
|
|
}
|
|
|
|
if (avail == NULL)
|
|
goto deadlock;
|
|
|
|
/* None available, try to steal one or wait for a user to finish */
|
|
list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
|
|
if (reg->pin_count)
|
|
continue;
|
|
|
|
return reg;
|
|
}
|
|
|
|
deadlock:
|
|
/* Wait for completion of pending flips which consume fences */
|
|
if (intel_has_pending_fb_unpin(dev))
|
|
return ERR_PTR(-EAGAIN);
|
|
|
|
return ERR_PTR(-EDEADLK);
|
|
}
|
|
|
|
/**
|
|
* i915_gem_object_get_fence - set up fencing for an object
|
|
* @obj: object to map through a fence reg
|
|
*
|
|
* When mapping objects through the GTT, userspace wants to be able to write
|
|
* to them without having to worry about swizzling if the object is tiled.
|
|
* This function walks the fence regs looking for a free one for @obj,
|
|
* stealing one if it can't find any.
|
|
*
|
|
* It then sets up the reg based on the object's properties: address, pitch
|
|
* and tiling format.
|
|
*
|
|
* For an untiled surface, this removes any existing fence.
|
|
*
|
|
* Returns:
|
|
*
|
|
* 0 on success, negative error code on failure.
|
|
*/
|
|
int
|
|
i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
|
|
{
|
|
struct drm_device *dev = obj->base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
bool enable = obj->tiling_mode != I915_TILING_NONE;
|
|
struct drm_i915_fence_reg *reg;
|
|
int ret;
|
|
|
|
/* Have we updated the tiling parameters upon the object and so
|
|
* will need to serialise the write to the associated fence register?
|
|
*/
|
|
if (obj->fence_dirty) {
|
|
ret = i915_gem_object_wait_fence(obj);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* Just update our place in the LRU if our fence is getting reused. */
|
|
if (obj->fence_reg != I915_FENCE_REG_NONE) {
|
|
reg = &dev_priv->fence_regs[obj->fence_reg];
|
|
if (!obj->fence_dirty) {
|
|
list_move_tail(®->lru_list,
|
|
&dev_priv->mm.fence_list);
|
|
return 0;
|
|
}
|
|
} else if (enable) {
|
|
if (WARN_ON(!obj->map_and_fenceable))
|
|
return -EINVAL;
|
|
|
|
reg = i915_find_fence_reg(dev);
|
|
if (IS_ERR(reg))
|
|
return PTR_ERR(reg);
|
|
|
|
if (reg->obj) {
|
|
struct drm_i915_gem_object *old = reg->obj;
|
|
|
|
ret = i915_gem_object_wait_fence(old);
|
|
if (ret)
|
|
return ret;
|
|
|
|
i915_gem_object_fence_lost(old);
|
|
}
|
|
} else
|
|
return 0;
|
|
|
|
i915_gem_object_update_fence(obj, reg, enable);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* i915_gem_object_pin_fence - pin fencing state
|
|
* @obj: object to pin fencing for
|
|
*
|
|
* This pins the fencing state (whether tiled or untiled) to make sure the
|
|
* object is ready to be used as a scanout target. Fencing status must be
|
|
* synchronize first by calling i915_gem_object_get_fence():
|
|
*
|
|
* The resulting fence pin reference must be released again with
|
|
* i915_gem_object_unpin_fence().
|
|
*
|
|
* Returns:
|
|
*
|
|
* True if the object has a fence, false otherwise.
|
|
*/
|
|
bool
|
|
i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
|
|
{
|
|
if (obj->fence_reg != I915_FENCE_REG_NONE) {
|
|
struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
|
|
struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
|
|
|
|
WARN_ON(!ggtt_vma ||
|
|
dev_priv->fence_regs[obj->fence_reg].pin_count >
|
|
ggtt_vma->pin_count);
|
|
dev_priv->fence_regs[obj->fence_reg].pin_count++;
|
|
return true;
|
|
} else
|
|
return false;
|
|
}
|
|
|
|
/**
|
|
* i915_gem_object_unpin_fence - unpin fencing state
|
|
* @obj: object to unpin fencing for
|
|
*
|
|
* This releases the fence pin reference acquired through
|
|
* i915_gem_object_pin_fence. It will handle both objects with and without an
|
|
* attached fence correctly, callers do not need to distinguish this.
|
|
*/
|
|
void
|
|
i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
|
|
{
|
|
if (obj->fence_reg != I915_FENCE_REG_NONE) {
|
|
struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
|
|
WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
|
|
dev_priv->fence_regs[obj->fence_reg].pin_count--;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* i915_gem_restore_fences - restore fence state
|
|
* @dev: DRM device
|
|
*
|
|
* Restore the hw fence state to match the software tracking again, to be called
|
|
* after a gpu reset and on resume.
|
|
*/
|
|
void i915_gem_restore_fences(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
int i;
|
|
|
|
for (i = 0; i < dev_priv->num_fence_regs; i++) {
|
|
struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
|
|
|
|
/*
|
|
* Commit delayed tiling changes if we have an object still
|
|
* attached to the fence, otherwise just clear the fence.
|
|
*/
|
|
if (reg->obj) {
|
|
i915_gem_object_update_fence(reg->obj, reg,
|
|
reg->obj->tiling_mode);
|
|
} else {
|
|
i915_gem_write_fence(dev, i, NULL);
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* DOC: tiling swizzling details
|
|
*
|
|
* The idea behind tiling is to increase cache hit rates by rearranging
|
|
* pixel data so that a group of pixel accesses are in the same cacheline.
|
|
* Performance improvement from doing this on the back/depth buffer are on
|
|
* the order of 30%.
|
|
*
|
|
* Intel architectures make this somewhat more complicated, though, by
|
|
* adjustments made to addressing of data when the memory is in interleaved
|
|
* mode (matched pairs of DIMMS) to improve memory bandwidth.
|
|
* For interleaved memory, the CPU sends every sequential 64 bytes
|
|
* to an alternate memory channel so it can get the bandwidth from both.
|
|
*
|
|
* The GPU also rearranges its accesses for increased bandwidth to interleaved
|
|
* memory, and it matches what the CPU does for non-tiled. However, when tiled
|
|
* it does it a little differently, since one walks addresses not just in the
|
|
* X direction but also Y. So, along with alternating channels when bit
|
|
* 6 of the address flips, it also alternates when other bits flip -- Bits 9
|
|
* (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
|
|
* are common to both the 915 and 965-class hardware.
|
|
*
|
|
* The CPU also sometimes XORs in higher bits as well, to improve
|
|
* bandwidth doing strided access like we do so frequently in graphics. This
|
|
* is called "Channel XOR Randomization" in the MCH documentation. The result
|
|
* is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
|
|
* decode.
|
|
*
|
|
* All of this bit 6 XORing has an effect on our memory management,
|
|
* as we need to make sure that the 3d driver can correctly address object
|
|
* contents.
|
|
*
|
|
* If we don't have interleaved memory, all tiling is safe and no swizzling is
|
|
* required.
|
|
*
|
|
* When bit 17 is XORed in, we simply refuse to tile at all. Bit
|
|
* 17 is not just a page offset, so as we page an object out and back in,
|
|
* individual pages in it will have different bit 17 addresses, resulting in
|
|
* each 64 bytes being swapped with its neighbor!
|
|
*
|
|
* Otherwise, if interleaved, we have to tell the 3d driver what the address
|
|
* swizzling it needs to do is, since it's writing with the CPU to the pages
|
|
* (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
|
|
* pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
|
|
* required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
|
|
* to match what the GPU expects.
|
|
*/
|
|
|
|
/**
|
|
* i915_gem_detect_bit_6_swizzle - detect bit 6 swizzling pattern
|
|
* @dev: DRM device
|
|
*
|
|
* Detects bit 6 swizzling of address lookup between IGD access and CPU
|
|
* access through main memory.
|
|
*/
|
|
void
|
|
i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
|
|
uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
|
|
|
|
if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
|
|
/*
|
|
* On BDW+, swizzling is not used. We leave the CPU memory
|
|
* controller in charge of optimizing memory accesses without
|
|
* the extra address manipulation GPU side.
|
|
*
|
|
* VLV and CHV don't have GPU swizzling.
|
|
*/
|
|
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
|
} else if (INTEL_INFO(dev)->gen >= 6) {
|
|
if (dev_priv->preserve_bios_swizzle) {
|
|
if (I915_READ(DISP_ARB_CTL) &
|
|
DISP_TILE_SURFACE_SWIZZLING) {
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9;
|
|
} else {
|
|
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
|
}
|
|
} else {
|
|
uint32_t dimm_c0, dimm_c1;
|
|
dimm_c0 = I915_READ(MAD_DIMM_C0);
|
|
dimm_c1 = I915_READ(MAD_DIMM_C1);
|
|
dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
|
|
dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
|
|
/* Enable swizzling when the channels are populated
|
|
* with identically sized dimms. We don't need to check
|
|
* the 3rd channel because no cpu with gpu attached
|
|
* ships in that configuration. Also, swizzling only
|
|
* makes sense for 2 channels anyway. */
|
|
if (dimm_c0 == dimm_c1) {
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9;
|
|
} else {
|
|
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
|
}
|
|
}
|
|
} else if (IS_GEN5(dev)) {
|
|
/* On Ironlake whatever DRAM config, GPU always do
|
|
* same swizzling setup.
|
|
*/
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9;
|
|
} else if (IS_GEN2(dev)) {
|
|
/* As far as we know, the 865 doesn't have these bit 6
|
|
* swizzling issues.
|
|
*/
|
|
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
|
} else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
|
|
uint32_t dcc;
|
|
|
|
/* On 9xx chipsets, channel interleave by the CPU is
|
|
* determined by DCC. For single-channel, neither the CPU
|
|
* nor the GPU do swizzling. For dual channel interleaved,
|
|
* the GPU's interleave is bit 9 and 10 for X tiled, and bit
|
|
* 9 for Y tiled. The CPU's interleave is independent, and
|
|
* can be based on either bit 11 (haven't seen this yet) or
|
|
* bit 17 (common).
|
|
*/
|
|
dcc = I915_READ(DCC);
|
|
switch (dcc & DCC_ADDRESSING_MODE_MASK) {
|
|
case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
|
|
case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
|
|
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
|
break;
|
|
case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
|
|
if (dcc & DCC_CHANNEL_XOR_DISABLE) {
|
|
/* This is the base swizzling by the GPU for
|
|
* tiled buffers.
|
|
*/
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9;
|
|
} else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
|
|
/* Bit 11 swizzling by the CPU in addition. */
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9_11;
|
|
} else {
|
|
/* Bit 17 swizzling by the CPU in addition. */
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9_17;
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* check for L-shaped memory aka modified enhanced addressing */
|
|
if (IS_GEN4(dev) &&
|
|
!(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
|
|
swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
|
|
}
|
|
|
|
if (dcc == 0xffffffff) {
|
|
DRM_ERROR("Couldn't read from MCHBAR. "
|
|
"Disabling tiling.\n");
|
|
swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
|
|
}
|
|
} else {
|
|
/* The 965, G33, and newer, have a very flexible memory
|
|
* configuration. It will enable dual-channel mode
|
|
* (interleaving) on as much memory as it can, and the GPU
|
|
* will additionally sometimes enable different bit 6
|
|
* swizzling for tiled objects from the CPU.
|
|
*
|
|
* Here's what I found on the G965:
|
|
* slot fill memory size swizzling
|
|
* 0A 0B 1A 1B 1-ch 2-ch
|
|
* 512 0 0 0 512 0 O
|
|
* 512 0 512 0 16 1008 X
|
|
* 512 0 0 512 16 1008 X
|
|
* 0 512 0 512 16 1008 X
|
|
* 1024 1024 1024 0 2048 1024 O
|
|
*
|
|
* We could probably detect this based on either the DRB
|
|
* matching, which was the case for the swizzling required in
|
|
* the table above, or from the 1-ch value being less than
|
|
* the minimum size of a rank.
|
|
*
|
|
* Reports indicate that the swizzling actually
|
|
* varies depending upon page placement inside the
|
|
* channels, i.e. we see swizzled pages where the
|
|
* banks of memory are paired and unswizzled on the
|
|
* uneven portion, so leave that as unknown.
|
|
*/
|
|
if (I915_READ16(C0DRB3) == I915_READ16(C1DRB3)) {
|
|
swizzle_x = I915_BIT_6_SWIZZLE_9_10;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_9;
|
|
}
|
|
}
|
|
|
|
if (swizzle_x == I915_BIT_6_SWIZZLE_UNKNOWN ||
|
|
swizzle_y == I915_BIT_6_SWIZZLE_UNKNOWN) {
|
|
/* Userspace likes to explode if it sees unknown swizzling,
|
|
* so lie. We will finish the lie when reporting through
|
|
* the get-tiling-ioctl by reporting the physical swizzle
|
|
* mode as unknown instead.
|
|
*
|
|
* As we don't strictly know what the swizzling is, it may be
|
|
* bit17 dependent, and so we need to also prevent the pages
|
|
* from being moved.
|
|
*/
|
|
dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
|
|
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
|
|
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
|
|
}
|
|
|
|
dev_priv->mm.bit_6_swizzle_x = swizzle_x;
|
|
dev_priv->mm.bit_6_swizzle_y = swizzle_y;
|
|
}
|
|
|
|
/*
|
|
* Swap every 64 bytes of this page around, to account for it having a new
|
|
* bit 17 of its physical address and therefore being interpreted differently
|
|
* by the GPU.
|
|
*/
|
|
static void
|
|
i915_gem_swizzle_page(struct page *page)
|
|
{
|
|
char temp[64];
|
|
char *vaddr;
|
|
int i;
|
|
|
|
vaddr = kmap(page);
|
|
|
|
for (i = 0; i < PAGE_SIZE; i += 128) {
|
|
memcpy(temp, &vaddr[i], 64);
|
|
memcpy(&vaddr[i], &vaddr[i + 64], 64);
|
|
memcpy(&vaddr[i + 64], temp, 64);
|
|
}
|
|
|
|
kunmap(page);
|
|
}
|
|
|
|
/**
|
|
* i915_gem_object_do_bit_17_swizzle - fixup bit 17 swizzling
|
|
* @obj: i915 GEM buffer object
|
|
*
|
|
* This function fixes up the swizzling in case any page frame number for this
|
|
* object has changed in bit 17 since that state has been saved with
|
|
* i915_gem_object_save_bit_17_swizzle().
|
|
*
|
|
* This is called when pinning backing storage again, since the kernel is free
|
|
* to move unpinned backing storage around (either by directly moving pages or
|
|
* by swapping them out and back in again).
|
|
*/
|
|
void
|
|
i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
|
|
{
|
|
struct sgt_iter sgt_iter;
|
|
struct page *page;
|
|
int i;
|
|
|
|
if (obj->bit_17 == NULL)
|
|
return;
|
|
|
|
i = 0;
|
|
for_each_sgt_page(page, sgt_iter, obj->pages) {
|
|
char new_bit_17 = page_to_phys(page) >> 17;
|
|
if ((new_bit_17 & 0x1) !=
|
|
(test_bit(i, obj->bit_17) != 0)) {
|
|
i915_gem_swizzle_page(page);
|
|
set_page_dirty(page);
|
|
}
|
|
i++;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* i915_gem_object_save_bit_17_swizzle - save bit 17 swizzling
|
|
* @obj: i915 GEM buffer object
|
|
*
|
|
* This function saves the bit 17 of each page frame number so that swizzling
|
|
* can be fixed up later on with i915_gem_object_do_bit_17_swizzle(). This must
|
|
* be called before the backing storage can be unpinned.
|
|
*/
|
|
void
|
|
i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
|
|
{
|
|
struct sgt_iter sgt_iter;
|
|
struct page *page;
|
|
int page_count = obj->base.size >> PAGE_SHIFT;
|
|
int i;
|
|
|
|
if (obj->bit_17 == NULL) {
|
|
obj->bit_17 = kcalloc(BITS_TO_LONGS(page_count),
|
|
sizeof(long), GFP_KERNEL);
|
|
if (obj->bit_17 == NULL) {
|
|
DRM_ERROR("Failed to allocate memory for bit 17 "
|
|
"record\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
i = 0;
|
|
|
|
for_each_sgt_page(page, sgt_iter, obj->pages) {
|
|
if (page_to_phys(page) & (1 << 17))
|
|
__set_bit(i, obj->bit_17);
|
|
else
|
|
__clear_bit(i, obj->bit_17);
|
|
i++;
|
|
}
|
|
}
|