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![Chris Wilson](/assets/img/avatar_default.png)
Introduced a new vm specfic callback insert_page() to program a single pte in ggtt or ppgtt. This allows us to map a single page in to the mappable aperture space. This can be iterated over to access the whole object by using space as meagre as page size. v2: Added low level rpm assertions to insert_page routines (Chris) v3: Added POSTING_READ post register write (Tvrtko) v4: Rebase (Ankit) v5: Removed wmb() and FLUSH_CTL from insert_page, caller to take care of it (Chris) v6: insert_page not working correctly without FLSH_CNTL write, added the write again. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ankitprasad Sharma <ankitprasad.r.sharma@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
601 lines
19 KiB
C
601 lines
19 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Please try to maintain the following order within this file unless it makes
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* sense to do otherwise. From top to bottom:
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* 1. typedefs
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* 2. #defines, and macros
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* 3. structure definitions
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* 4. function prototypes
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*
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* Within each section, please try to order by generation in ascending order,
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* from top to bottom (ie. gen6 on the top, gen8 on the bottom).
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*/
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#ifndef __I915_GEM_GTT_H__
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#define __I915_GEM_GTT_H__
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#include <linux/io-mapping.h>
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struct drm_i915_file_private;
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typedef uint32_t gen6_pte_t;
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typedef uint64_t gen8_pte_t;
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typedef uint64_t gen8_pde_t;
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typedef uint64_t gen8_ppgtt_pdpe_t;
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typedef uint64_t gen8_ppgtt_pml4e_t;
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#define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT)
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/* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
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#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
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#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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#define GEN6_PTE_CACHE_LLC (2 << 1)
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#define GEN6_PTE_UNCACHED (1 << 1)
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#define GEN6_PTE_VALID (1 << 0)
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#define I915_PTES(pte_len) (PAGE_SIZE / (pte_len))
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#define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
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#define I915_PDES 512
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#define I915_PDE_MASK (I915_PDES - 1)
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#define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
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#define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
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#define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
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#define GEN6_PD_ALIGN (PAGE_SIZE * 16)
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#define GEN6_PDE_SHIFT 22
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#define GEN6_PDE_VALID (1 << 0)
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#define GEN7_PTE_CACHE_L3_LLC (3 << 1)
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#define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
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#define BYT_PTE_WRITEABLE (1 << 1)
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/* Cacheability Control is a 4-bit value. The low three bits are stored in bits
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* 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
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*/
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#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
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(((bits) & 0x8) << (11 - 3)))
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#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
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#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
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#define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
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#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
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#define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
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#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
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#define HSW_PTE_UNCACHED (0)
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#define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
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#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
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/* GEN8 legacy style address is defined as a 3 level page table:
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* 31:30 | 29:21 | 20:12 | 11:0
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* PDPE | PDE | PTE | offset
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* The difference as compared to normal x86 3 level page table is the PDPEs are
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* programmed via register.
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*
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* GEN8 48b legacy style address is defined as a 4 level page table:
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* 47:39 | 38:30 | 29:21 | 20:12 | 11:0
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* PML4E | PDPE | PDE | PTE | offset
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*/
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#define GEN8_PML4ES_PER_PML4 512
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#define GEN8_PML4E_SHIFT 39
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#define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1)
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#define GEN8_PDPE_SHIFT 30
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/* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
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* tables */
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#define GEN8_PDPE_MASK 0x1ff
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#define GEN8_PDE_SHIFT 21
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#define GEN8_PDE_MASK 0x1ff
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#define GEN8_PTE_SHIFT 12
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#define GEN8_PTE_MASK 0x1ff
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#define GEN8_LEGACY_PDPES 4
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#define GEN8_PTES I915_PTES(sizeof(gen8_pte_t))
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#define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
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GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES)
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#define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
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#define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
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#define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
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#define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
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#define CHV_PPAT_SNOOP (1<<6)
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#define GEN8_PPAT_AGE(x) (x<<4)
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#define GEN8_PPAT_LLCeLLC (3<<2)
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#define GEN8_PPAT_LLCELLC (2<<2)
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#define GEN8_PPAT_LLC (1<<2)
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#define GEN8_PPAT_WB (3<<0)
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#define GEN8_PPAT_WT (2<<0)
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#define GEN8_PPAT_WC (1<<0)
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#define GEN8_PPAT_UC (0<<0)
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#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
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#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
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enum i915_ggtt_view_type {
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I915_GGTT_VIEW_NORMAL = 0,
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I915_GGTT_VIEW_ROTATED,
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I915_GGTT_VIEW_PARTIAL,
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};
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struct intel_rotation_info {
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unsigned int uv_offset;
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uint32_t pixel_format;
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unsigned int uv_start_page;
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struct {
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/* tiles */
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unsigned int width, height;
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} plane[2];
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};
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struct i915_ggtt_view {
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enum i915_ggtt_view_type type;
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union {
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struct {
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u64 offset;
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unsigned int size;
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} partial;
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struct intel_rotation_info rotated;
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} params;
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struct sg_table *pages;
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};
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extern const struct i915_ggtt_view i915_ggtt_view_normal;
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extern const struct i915_ggtt_view i915_ggtt_view_rotated;
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enum i915_cache_level;
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/**
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* A VMA represents a GEM BO that is bound into an address space. Therefore, a
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* VMA's presence cannot be guaranteed before binding, or after unbinding the
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* object into/from the address space.
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*
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* To make things as simple as possible (ie. no refcounting), a VMA's lifetime
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* will always be <= an objects lifetime. So object refcounting should cover us.
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*/
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struct i915_vma {
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struct drm_mm_node node;
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struct drm_i915_gem_object *obj;
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struct i915_address_space *vm;
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void __iomem *iomap;
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/** Flags and address space this VMA is bound to */
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#define GLOBAL_BIND (1<<0)
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#define LOCAL_BIND (1<<1)
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unsigned int bound : 4;
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bool is_ggtt : 1;
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/**
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* Support different GGTT views into the same object.
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* This means there can be multiple VMA mappings per object and per VM.
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* i915_ggtt_view_type is used to distinguish between those entries.
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* The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also
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* assumed in GEM functions which take no ggtt view parameter.
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*/
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struct i915_ggtt_view ggtt_view;
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/** This object's place on the active/inactive lists */
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struct list_head vm_link;
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struct list_head obj_link; /* Link in the object's VMA list */
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/** This vma's place in the batchbuffer or on the eviction list */
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struct list_head exec_list;
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/**
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* Used for performing relocations during execbuffer insertion.
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*/
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struct hlist_node exec_node;
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unsigned long exec_handle;
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struct drm_i915_gem_exec_object2 *exec_entry;
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/**
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* How many users have pinned this object in GTT space. The following
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* users can each hold at most one reference: pwrite/pread, execbuffer
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* (objects are not allowed multiple times for the same batchbuffer),
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* and the framebuffer code. When switching/pageflipping, the
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* framebuffer code has at most two buffers pinned per crtc.
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*
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* In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
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* bits with absolutely no headroom. So use 4 bits. */
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unsigned int pin_count:4;
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#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
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};
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struct i915_page_dma {
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struct page *page;
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union {
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dma_addr_t daddr;
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/* For gen6/gen7 only. This is the offset in the GGTT
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* where the page directory entries for PPGTT begin
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*/
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uint32_t ggtt_offset;
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};
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};
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#define px_base(px) (&(px)->base)
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#define px_page(px) (px_base(px)->page)
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#define px_dma(px) (px_base(px)->daddr)
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struct i915_page_scratch {
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struct i915_page_dma base;
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};
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struct i915_page_table {
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struct i915_page_dma base;
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unsigned long *used_ptes;
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};
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struct i915_page_directory {
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struct i915_page_dma base;
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unsigned long *used_pdes;
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struct i915_page_table *page_table[I915_PDES]; /* PDEs */
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};
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struct i915_page_directory_pointer {
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struct i915_page_dma base;
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unsigned long *used_pdpes;
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struct i915_page_directory **page_directory;
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};
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struct i915_pml4 {
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struct i915_page_dma base;
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DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4);
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struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4];
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};
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struct i915_address_space {
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struct drm_mm mm;
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struct drm_device *dev;
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struct list_head global_link;
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u64 start; /* Start offset always 0 for dri2 */
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u64 total; /* size addr space maps (ex. 2GB for ggtt) */
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bool is_ggtt;
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struct i915_page_scratch *scratch_page;
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struct i915_page_table *scratch_pt;
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struct i915_page_directory *scratch_pd;
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struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */
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/**
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* List of objects currently involved in rendering.
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*
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* Includes buffers having the contents of their GPU caches
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* flushed, not necessarily primitives. last_read_req
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* represents when the rendering involved will be completed.
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*
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* A reference is held on the buffer while on this list.
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*/
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struct list_head active_list;
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/**
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* LRU list of objects which are not in the ringbuffer and
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* are ready to unbind, but are still in the GTT.
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*
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* last_read_req is NULL while an object is in this list.
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*
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* A reference is not held on the buffer while on this list,
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* as merely being GTT-bound shouldn't prevent its being
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* freed, and we'll pull it off the list in the free path.
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*/
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struct list_head inactive_list;
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/* FIXME: Need a more generic return type */
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gen6_pte_t (*pte_encode)(dma_addr_t addr,
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enum i915_cache_level level,
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bool valid, u32 flags); /* Create a valid PTE */
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/* flags for pte_encode */
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#define PTE_READ_ONLY (1<<0)
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int (*allocate_va_range)(struct i915_address_space *vm,
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uint64_t start,
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uint64_t length);
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void (*clear_range)(struct i915_address_space *vm,
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uint64_t start,
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uint64_t length,
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bool use_scratch);
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void (*insert_page)(struct i915_address_space *vm,
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dma_addr_t addr,
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uint64_t offset,
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enum i915_cache_level cache_level,
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u32 flags);
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void (*insert_entries)(struct i915_address_space *vm,
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struct sg_table *st,
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uint64_t start,
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enum i915_cache_level cache_level, u32 flags);
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void (*cleanup)(struct i915_address_space *vm);
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/** Unmap an object from an address space. This usually consists of
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* setting the valid PTE entries to a reserved scratch page. */
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void (*unbind_vma)(struct i915_vma *vma);
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/* Map an object into an address space with the given cache flags. */
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int (*bind_vma)(struct i915_vma *vma,
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enum i915_cache_level cache_level,
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u32 flags);
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};
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#define i915_is_ggtt(V) ((V)->is_ggtt)
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/* The Graphics Translation Table is the way in which GEN hardware translates a
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* Graphics Virtual Address into a Physical Address. In addition to the normal
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* collateral associated with any va->pa translations GEN hardware also has a
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* portion of the GTT which can be mapped by the CPU and remain both coherent
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* and correct (in cases like swizzling). That region is referred to as GMADR in
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* the spec.
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*/
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struct i915_ggtt {
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struct i915_address_space base;
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size_t stolen_size; /* Total size of stolen memory */
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size_t stolen_usable_size; /* Total size minus BIOS reserved */
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size_t stolen_reserved_base;
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size_t stolen_reserved_size;
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size_t size; /* Total size of Global GTT */
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u64 mappable_end; /* End offset that we can CPU map */
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struct io_mapping *mappable; /* Mapping to our CPU mappable region */
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phys_addr_t mappable_base; /* PA of our GMADR */
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/** "Graphics Stolen Memory" holds the global PTEs */
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void __iomem *gsm;
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bool do_idle_maps;
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int mtrr;
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int (*probe)(struct i915_ggtt *ggtt);
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};
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struct i915_hw_ppgtt {
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struct i915_address_space base;
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struct kref ref;
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struct drm_mm_node node;
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unsigned long pd_dirty_rings;
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union {
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struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */
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struct i915_page_directory_pointer pdp; /* GEN8+ */
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struct i915_page_directory pd; /* GEN6-7 */
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};
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struct drm_i915_file_private *file_priv;
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gen6_pte_t __iomem *pd_addr;
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int (*enable)(struct i915_hw_ppgtt *ppgtt);
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int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
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struct drm_i915_gem_request *req);
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void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
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};
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/* For each pde iterates over every pde between from start until start + length.
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* If start, and start+length are not perfectly divisible, the macro will round
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* down, and up as needed. The macro modifies pde, start, and length. Dev is
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* only used to differentiate shift values. Temp is temp. On gen6/7, start = 0,
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* and length = 2G effectively iterates over every PDE in the system.
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*
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* XXX: temp is not actually needed, but it saves doing the ALIGN operation.
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*/
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#define gen6_for_each_pde(pt, pd, start, length, temp, iter) \
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for (iter = gen6_pde_index(start); \
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length > 0 && iter < I915_PDES ? \
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(pt = (pd)->page_table[iter]), 1 : 0; \
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iter++, \
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temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \
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temp = min_t(unsigned, temp, length), \
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start += temp, length -= temp)
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#define gen6_for_all_pdes(pt, ppgtt, iter) \
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for (iter = 0; \
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pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \
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iter++)
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static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift)
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{
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const uint32_t mask = NUM_PTE(pde_shift) - 1;
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return (address >> PAGE_SHIFT) & mask;
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}
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/* Helper to counts the number of PTEs within the given length. This count
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* does not cross a page table boundary, so the max value would be
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* GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
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*/
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static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
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uint32_t pde_shift)
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{
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const uint64_t mask = ~((1ULL << pde_shift) - 1);
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uint64_t end;
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WARN_ON(length == 0);
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WARN_ON(offset_in_page(addr|length));
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end = addr + length;
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if ((addr & mask) != (end & mask))
|
|
return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
|
|
|
|
return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
|
|
}
|
|
|
|
static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift)
|
|
{
|
|
return (addr >> shift) & I915_PDE_MASK;
|
|
}
|
|
|
|
static inline uint32_t gen6_pte_index(uint32_t addr)
|
|
{
|
|
return i915_pte_index(addr, GEN6_PDE_SHIFT);
|
|
}
|
|
|
|
static inline size_t gen6_pte_count(uint32_t addr, uint32_t length)
|
|
{
|
|
return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
|
|
}
|
|
|
|
static inline uint32_t gen6_pde_index(uint32_t addr)
|
|
{
|
|
return i915_pde_index(addr, GEN6_PDE_SHIFT);
|
|
}
|
|
|
|
/* Equivalent to the gen6 version, For each pde iterates over every pde
|
|
* between from start until start + length. On gen8+ it simply iterates
|
|
* over every page directory entry in a page directory.
|
|
*/
|
|
#define gen8_for_each_pde(pt, pd, start, length, iter) \
|
|
for (iter = gen8_pde_index(start); \
|
|
length > 0 && iter < I915_PDES && \
|
|
(pt = (pd)->page_table[iter], true); \
|
|
({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \
|
|
temp = min(temp - start, length); \
|
|
start += temp, length -= temp; }), ++iter)
|
|
|
|
#define gen8_for_each_pdpe(pd, pdp, start, length, iter) \
|
|
for (iter = gen8_pdpe_index(start); \
|
|
length > 0 && iter < I915_PDPES_PER_PDP(dev) && \
|
|
(pd = (pdp)->page_directory[iter], true); \
|
|
({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \
|
|
temp = min(temp - start, length); \
|
|
start += temp, length -= temp; }), ++iter)
|
|
|
|
#define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \
|
|
for (iter = gen8_pml4e_index(start); \
|
|
length > 0 && iter < GEN8_PML4ES_PER_PML4 && \
|
|
(pdp = (pml4)->pdps[iter], true); \
|
|
({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \
|
|
temp = min(temp - start, length); \
|
|
start += temp, length -= temp; }), ++iter)
|
|
|
|
static inline uint32_t gen8_pte_index(uint64_t address)
|
|
{
|
|
return i915_pte_index(address, GEN8_PDE_SHIFT);
|
|
}
|
|
|
|
static inline uint32_t gen8_pde_index(uint64_t address)
|
|
{
|
|
return i915_pde_index(address, GEN8_PDE_SHIFT);
|
|
}
|
|
|
|
static inline uint32_t gen8_pdpe_index(uint64_t address)
|
|
{
|
|
return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
|
|
}
|
|
|
|
static inline uint32_t gen8_pml4e_index(uint64_t address)
|
|
{
|
|
return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK;
|
|
}
|
|
|
|
static inline size_t gen8_pte_count(uint64_t address, uint64_t length)
|
|
{
|
|
return i915_pte_count(address, length, GEN8_PDE_SHIFT);
|
|
}
|
|
|
|
static inline dma_addr_t
|
|
i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
|
|
{
|
|
return test_bit(n, ppgtt->pdp.used_pdpes) ?
|
|
px_dma(ppgtt->pdp.page_directory[n]) :
|
|
px_dma(ppgtt->base.scratch_pd);
|
|
}
|
|
|
|
int i915_ggtt_init_hw(struct drm_device *dev);
|
|
int i915_ggtt_enable_hw(struct drm_device *dev);
|
|
void i915_gem_init_ggtt(struct drm_device *dev);
|
|
void i915_ggtt_cleanup_hw(struct drm_device *dev);
|
|
|
|
int i915_ppgtt_init_hw(struct drm_device *dev);
|
|
void i915_ppgtt_release(struct kref *kref);
|
|
struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev,
|
|
struct drm_i915_file_private *fpriv);
|
|
static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
|
|
{
|
|
if (ppgtt)
|
|
kref_get(&ppgtt->ref);
|
|
}
|
|
static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
|
|
{
|
|
if (ppgtt)
|
|
kref_put(&ppgtt->ref, i915_ppgtt_release);
|
|
}
|
|
|
|
void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
|
|
void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
|
|
void i915_gem_restore_gtt_mappings(struct drm_device *dev);
|
|
|
|
int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
|
|
void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
|
|
|
|
static inline bool
|
|
i915_ggtt_view_equal(const struct i915_ggtt_view *a,
|
|
const struct i915_ggtt_view *b)
|
|
{
|
|
if (WARN_ON(!a || !b))
|
|
return false;
|
|
|
|
if (a->type != b->type)
|
|
return false;
|
|
if (a->type != I915_GGTT_VIEW_NORMAL)
|
|
return !memcmp(&a->params, &b->params, sizeof(a->params));
|
|
return true;
|
|
}
|
|
|
|
size_t
|
|
i915_ggtt_view_size(struct drm_i915_gem_object *obj,
|
|
const struct i915_ggtt_view *view);
|
|
|
|
/**
|
|
* i915_vma_pin_iomap - calls ioremap_wc to map the GGTT VMA via the aperture
|
|
* @vma: VMA to iomap
|
|
*
|
|
* The passed in VMA has to be pinned in the global GTT mappable region.
|
|
* An extra pinning of the VMA is acquired for the return iomapping,
|
|
* the caller must call i915_vma_unpin_iomap to relinquish the pinning
|
|
* after the iomapping is no longer required.
|
|
*
|
|
* Callers must hold the struct_mutex.
|
|
*
|
|
* Returns a valid iomapped pointer or ERR_PTR.
|
|
*/
|
|
void __iomem *i915_vma_pin_iomap(struct i915_vma *vma);
|
|
|
|
/**
|
|
* i915_vma_unpin_iomap - unpins the mapping returned from i915_vma_iomap
|
|
* @vma: VMA to unpin
|
|
*
|
|
* Unpins the previously iomapped VMA from i915_vma_pin_iomap().
|
|
*
|
|
* Callers must hold the struct_mutex. This function is only valid to be
|
|
* called on a VMA previously iomapped by the caller with i915_vma_pin_iomap().
|
|
*/
|
|
static inline void i915_vma_unpin_iomap(struct i915_vma *vma)
|
|
{
|
|
lockdep_assert_held(&vma->vm->dev->struct_mutex);
|
|
GEM_BUG_ON(vma->pin_count == 0);
|
|
GEM_BUG_ON(vma->iomap == NULL);
|
|
vma->pin_count--;
|
|
}
|
|
|
|
#endif
|