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![John Crispin](/assets/img/avatar_default.png)
The old address is no longer valid. Use the my new one instead. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13201/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
353 lines
5.4 KiB
C
353 lines
5.4 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <john@phrozen.org>
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* Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
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*/
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#include <linux/io.h>
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#include <linux/export.h>
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#include <linux/clk.h>
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#include <asm/time.h>
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#include <asm/irq.h>
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#include <asm/div64.h>
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#include <lantiq_soc.h>
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#include "../clk.h"
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static unsigned int ram_clocks[] = {
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CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
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#define DDR_HZ ram_clocks[ltq_cgu_r32(CGU_SYS) & 0x3]
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/* legacy xway clock */
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#define CGU_SYS 0x10
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/* vr9, ar10/grx390 clock */
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#define CGU_SYS_XRX 0x0c
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#define CGU_IF_CLK_AR10 0x24
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unsigned long ltq_danube_fpi_hz(void)
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{
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unsigned long ddr_clock = DDR_HZ;
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if (ltq_cgu_r32(CGU_SYS) & 0x40)
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return ddr_clock >> 1;
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return ddr_clock;
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}
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unsigned long ltq_danube_cpu_hz(void)
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{
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switch (ltq_cgu_r32(CGU_SYS) & 0xc) {
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case 0:
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return CLOCK_333M;
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case 4:
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return DDR_HZ;
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case 8:
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return DDR_HZ << 1;
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default:
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return DDR_HZ >> 1;
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}
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}
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unsigned long ltq_danube_pp32_hz(void)
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{
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unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
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unsigned long clk;
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switch (clksys) {
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case 1:
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clk = CLOCK_240M;
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break;
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case 2:
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clk = CLOCK_222M;
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break;
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case 3:
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clk = CLOCK_133M;
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break;
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default:
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clk = CLOCK_266M;
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break;
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}
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return clk;
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}
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unsigned long ltq_ar9_sys_hz(void)
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{
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if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
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return CLOCK_393M;
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return CLOCK_333M;
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}
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unsigned long ltq_ar9_fpi_hz(void)
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{
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unsigned long sys = ltq_ar9_sys_hz();
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if (ltq_cgu_r32(CGU_SYS) & BIT(0))
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return sys / 3;
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else
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return sys / 2;
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}
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unsigned long ltq_ar9_cpu_hz(void)
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{
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if (ltq_cgu_r32(CGU_SYS) & BIT(2))
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return ltq_ar9_fpi_hz();
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else
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return ltq_ar9_sys_hz();
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}
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unsigned long ltq_vr9_cpu_hz(void)
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{
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unsigned int cpu_sel;
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unsigned long clk;
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cpu_sel = (ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0xf;
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switch (cpu_sel) {
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case 0:
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clk = CLOCK_600M;
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break;
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case 1:
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clk = CLOCK_500M;
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break;
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case 2:
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clk = CLOCK_393M;
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break;
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case 3:
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clk = CLOCK_333M;
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break;
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case 5:
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case 6:
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clk = CLOCK_196_608M;
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break;
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case 7:
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clk = CLOCK_167M;
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break;
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case 4:
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case 8:
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case 9:
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clk = CLOCK_125M;
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break;
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default:
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clk = 0;
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break;
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}
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return clk;
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}
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unsigned long ltq_vr9_fpi_hz(void)
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{
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unsigned int ocp_sel, cpu_clk;
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unsigned long clk;
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cpu_clk = ltq_vr9_cpu_hz();
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ocp_sel = ltq_cgu_r32(CGU_SYS_XRX) & 0x3;
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switch (ocp_sel) {
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case 0:
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/* OCP ratio 1 */
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clk = cpu_clk;
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break;
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case 2:
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/* OCP ratio 2 */
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clk = cpu_clk / 2;
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break;
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case 3:
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/* OCP ratio 2.5 */
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clk = (cpu_clk * 2) / 5;
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break;
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case 4:
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/* OCP ratio 3 */
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clk = cpu_clk / 3;
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break;
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default:
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clk = 0;
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break;
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}
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return clk;
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}
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unsigned long ltq_vr9_pp32_hz(void)
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{
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unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
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unsigned long clk;
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switch (clksys) {
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case 0:
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clk = CLOCK_500M;
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break;
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case 1:
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clk = CLOCK_432M;
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break;
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case 2:
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clk = CLOCK_288M;
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break;
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default:
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clk = CLOCK_500M;
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break;
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}
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return clk;
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}
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unsigned long ltq_ar10_cpu_hz(void)
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{
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unsigned int clksys;
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int cpu_fs = (ltq_cgu_r32(CGU_SYS_XRX) >> 8) & 0x1;
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int freq_div = (ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0x7;
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switch (cpu_fs) {
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case 0:
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clksys = CLOCK_500M;
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break;
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case 1:
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clksys = CLOCK_600M;
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break;
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default:
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clksys = CLOCK_500M;
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break;
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}
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switch (freq_div) {
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case 0:
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return clksys;
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case 1:
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return clksys >> 1;
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case 2:
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return clksys >> 2;
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default:
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return clksys;
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}
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}
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unsigned long ltq_ar10_fpi_hz(void)
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{
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int freq_fpi = (ltq_cgu_r32(CGU_IF_CLK_AR10) >> 25) & 0xf;
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switch (freq_fpi) {
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case 1:
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return CLOCK_300M;
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case 5:
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return CLOCK_250M;
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case 2:
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return CLOCK_150M;
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case 6:
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return CLOCK_125M;
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default:
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return CLOCK_125M;
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}
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}
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unsigned long ltq_ar10_pp32_hz(void)
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{
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unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
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unsigned long clk;
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switch (clksys) {
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case 1:
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clk = CLOCK_250M;
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break;
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case 4:
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clk = CLOCK_400M;
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break;
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default:
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clk = CLOCK_250M;
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break;
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}
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return clk;
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}
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unsigned long ltq_grx390_cpu_hz(void)
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{
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unsigned int clksys;
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int cpu_fs = ((ltq_cgu_r32(CGU_SYS_XRX) >> 9) & 0x3);
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int freq_div = ((ltq_cgu_r32(CGU_SYS_XRX) >> 4) & 0x7);
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switch (cpu_fs) {
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case 0:
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clksys = CLOCK_600M;
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break;
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case 1:
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clksys = CLOCK_666M;
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break;
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case 2:
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clksys = CLOCK_720M;
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break;
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default:
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clksys = CLOCK_600M;
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break;
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}
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switch (freq_div) {
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case 0:
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return clksys;
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case 1:
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return clksys >> 1;
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case 2:
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return clksys >> 2;
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default:
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return clksys;
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}
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}
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unsigned long ltq_grx390_fpi_hz(void)
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{
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/* fpi clock is derived from ddr_clk */
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unsigned int clksys;
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int cpu_fs = ((ltq_cgu_r32(CGU_SYS_XRX) >> 9) & 0x3);
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int freq_div = ((ltq_cgu_r32(CGU_SYS_XRX)) & 0x7);
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switch (cpu_fs) {
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case 0:
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clksys = CLOCK_600M;
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break;
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case 1:
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clksys = CLOCK_666M;
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break;
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case 2:
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clksys = CLOCK_720M;
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break;
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default:
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clksys = CLOCK_600M;
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break;
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}
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switch (freq_div) {
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case 1:
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return clksys >> 1;
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case 2:
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return clksys >> 2;
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default:
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return clksys >> 1;
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}
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}
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unsigned long ltq_grx390_pp32_hz(void)
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{
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unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;
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unsigned long clk;
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switch (clksys) {
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case 1:
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clk = CLOCK_250M;
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break;
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case 2:
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clk = CLOCK_432M;
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break;
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case 4:
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clk = CLOCK_400M;
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break;
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default:
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clk = CLOCK_250M;
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break;
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}
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return clk;
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}
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