Thierry Reding f679e89acd clk: tegra: Avoid calling an uninitialized function ... Commit 493ffb046c ("clk: tegra: super: Switch to determine_rate") replaced clk_super_round_rate() by clk_super_determine_rate(), but didn't update one callsite that was explicitly calling the old tegra_clk_super_ops.round_rate() function, which was now NULL. This resulted in a crash on Tegra30 systems during early boot. Switch this callsite over to the clk_super_determine_rate() equivalent to avoid the crash. Fixes: 493ffb046c ("clk: tegra: super: Switch to determine_rate") Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20230630130748.840729-1-thierry.reding@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2023-07-04 08:54:37 -07:00
..
clk-audio-sync.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-bpmp.c	clk: tegra: bpmp: Add a determine_rate hook	2023-06-08 18:39:30 -07:00
clk-device.c	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
clk-dfll.c	clk: tegra: Don't warn three times about failure to unregister	2023-03-28 19:23:35 -07:00
clk-dfll.h	clk: tegra: clk-dfll: Add suspend and resume support	2019-11-11 14:53:03 +01:00
clk-divider.c	clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation	2020-01-10 15:50:05 +01:00
clk-id.h	clk: tegra: Fix duplicated SE clock entry	2020-12-10 12:51:59 -08:00
clk-periph-fixed.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-periph-gate.c	clk: tegra: Don't deassert reset on enabling clocks	2021-05-31 15:16:46 +02:00
clk-periph.c	clk: tegra: periph: Switch to determine_rate	2023-06-08 18:39:35 -07:00
clk-pll-out.c	clk: tegra: pllout: Save and restore pllout context	2019-11-11 14:53:02 +01:00
clk-pll.c	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
clk-sdmmc-mux.c	clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops	2021-07-27 14:54:19 -07:00
clk-super.c	clk: tegra: super: Switch to determine_rate	2023-06-08 18:39:35 -07:00
clk-tegra-audio.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	2019-05-30 11:29:52 -07:00
clk-tegra-fixed.c	clk: tegra: Remove CLK_M_DIV fixed clocks	2020-03-12 11:33:32 +01:00
clk-tegra-periph.c	clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock	2021-08-11 11:57:01 +02:00
clk-tegra-super-cclk.c	clk: tegra: Avoid calling an uninitialized function	2023-07-04 08:54:37 -07:00
clk-tegra-super-gen4.c	clk: tegra: clk-super: Fix to enable PLLP branches to CPU	2019-11-11 14:53:03 +01:00
clk-tegra20-emc.c	clk: tegra: Export Tegra20 EMC kernel symbols	2020-11-06 19:24:04 +01:00
clk-tegra20.c	clk: tegra20: fix gcc-7 constant overflow warning	2023-03-29 15:32:25 -07:00
clk-tegra30.c	clk: tegra: Fix Tegra PWM parent clock	2022-10-14 13:44:24 -07:00
clk-tegra114.c	clk: tegra: Fix Tegra PWM parent clock	2022-10-14 13:44:24 -07:00
clk-tegra124-dfll-fcpu.c	clk: tegra: Convert to platform remove callback returning void	2023-03-28 19:31:45 -07:00
clk-tegra124-emc.c	clk: tegra: tegra124-emc: Fix potential memory leak	2023-06-14 18:25:51 -07:00
clk-tegra124.c	clk: tegra: Fix Tegra PWM parent clock	2022-10-14 13:44:24 -07:00
clk-tegra210-emc.c	This pull request contains zero diff to the core framework. It is a collection	2020-10-22 12:53:28 -07:00
clk-tegra210.c	clk: tegra: Fix Tegra PWM parent clock	2022-10-14 13:44:24 -07:00
clk-utils.c	clk: tegra: Refactor fractional divider calculation	2018-07-25 13:43:34 -07:00
clk.c	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
clk.h	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00
cvb.c	clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s align param	2021-02-11 11:56:05 -08:00
cvb.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
Kconfig	memory: tegra124-emc: Make driver modular	2021-01-05 18:00:09 +01:00
Makefile	clk: tegra: Support runtime PM and power domain	2021-12-15 18:55:21 +01:00