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![Peng Fan](/assets/img/avatar_default.png)
Because IMX_MU_xCR_MAX was increased to 5, some mu cfgs were not updated
to include the CR register. Add the missed CR register to xcr array.
Fixes: 82ab513bae
("mailbox: imx: support RST channel")
Reported-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Liu Ying <victor.liu@nxp.com> # i.MX8qm/qxp MEK boards boot
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
1057 lines
26 KiB
C
1057 lines
26 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
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* Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com>
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*/
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#include <linux/clk.h>
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#include <linux/firmware/imx/ipc.h>
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#include <linux/firmware/imx/s4.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/mailbox_controller.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/suspend.h>
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#include <linux/slab.h>
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#define IMX_MU_CHANS 17
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/* TX0/RX0/RXDB[0-3] */
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#define IMX_MU_SCU_CHANS 6
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/* TX0/RX0 */
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#define IMX_MU_S4_CHANS 2
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#define IMX_MU_CHAN_NAME_SIZE 20
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#define IMX_MU_NUM_RR 4
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#define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))
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#define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))
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/* Please not change TX & RX */
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enum imx_mu_chan_type {
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IMX_MU_TYPE_TX = 0, /* Tx */
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IMX_MU_TYPE_RX = 1, /* Rx */
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IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */
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IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */
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IMX_MU_TYPE_RST = 4, /* Reset */
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};
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enum imx_mu_xcr {
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IMX_MU_CR,
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IMX_MU_GIER,
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IMX_MU_GCR,
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IMX_MU_TCR,
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IMX_MU_RCR,
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IMX_MU_xCR_MAX,
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};
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enum imx_mu_xsr {
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IMX_MU_SR,
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IMX_MU_GSR,
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IMX_MU_TSR,
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IMX_MU_RSR,
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IMX_MU_xSR_MAX,
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};
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struct imx_sc_rpc_msg_max {
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struct imx_sc_rpc_msg hdr;
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u32 data[30];
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};
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struct imx_s4_rpc_msg_max {
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struct imx_s4_rpc_msg hdr;
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u32 data[254];
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};
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struct imx_mu_con_priv {
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unsigned int idx;
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char irq_desc[IMX_MU_CHAN_NAME_SIZE];
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enum imx_mu_chan_type type;
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struct mbox_chan *chan;
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struct tasklet_struct txdb_tasklet;
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};
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struct imx_mu_priv {
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struct device *dev;
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void __iomem *base;
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void *msg;
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spinlock_t xcr_lock; /* control register lock */
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struct mbox_controller mbox;
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struct mbox_chan mbox_chans[IMX_MU_CHANS];
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struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
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const struct imx_mu_dcfg *dcfg;
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struct clk *clk;
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int irq[IMX_MU_CHANS];
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bool suspend;
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u32 xcr[IMX_MU_xCR_MAX];
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bool side_b;
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};
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enum imx_mu_type {
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IMX_MU_V1,
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IMX_MU_V2 = BIT(1),
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IMX_MU_V2_S4 = BIT(15),
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IMX_MU_V2_IRQ = BIT(16),
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};
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struct imx_mu_dcfg {
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int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
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int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
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int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
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void (*init)(struct imx_mu_priv *priv);
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enum imx_mu_type type;
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u32 xTR; /* Transmit Register0 */
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u32 xRR; /* Receive Register0 */
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u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */
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u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */
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};
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#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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/* General Purpose Interrupt Enable */
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#define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
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/* Receive Interrupt Enable */
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#define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
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/* Transmit Interrupt Enable */
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#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
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/* General Purpose Interrupt Request */
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#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
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/* MU reset */
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#define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5))
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#define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7))
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static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
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{
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return container_of(mbox, struct imx_mu_priv, mbox);
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}
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static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
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{
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iowrite32(val, priv->base + offs);
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}
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static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
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{
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return ioread32(priv->base + offs);
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}
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static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx)
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{
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u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT;
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u32 status;
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u32 can_write;
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dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx);
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do {
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status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
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can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);
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} while (!can_write && time_is_after_jiffies64(timeout_time));
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if (!can_write) {
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dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n",
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val, idx, status);
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return -ETIME;
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}
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imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);
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return 0;
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}
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static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx)
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{
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u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT;
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u32 status;
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u32 can_read;
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dev_dbg(priv->dev, "Trying to read from idx %d\n", idx);
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do {
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status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
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can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);
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} while (!can_read && time_is_after_jiffies64(timeout_time));
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if (!can_read) {
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dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n",
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idx, status);
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return -ETIME;
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}
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*val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);
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dev_dbg(priv->dev, "Read %.8x\n", *val);
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return 0;
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}
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static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&priv->xcr_lock, flags);
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val = imx_mu_read(priv, priv->dcfg->xCR[type]);
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val &= ~clr;
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val |= set;
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imx_mu_write(priv, val, priv->dcfg->xCR[type]);
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spin_unlock_irqrestore(&priv->xcr_lock, flags);
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return val;
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}
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static int imx_mu_generic_tx(struct imx_mu_priv *priv,
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struct imx_mu_con_priv *cp,
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void *data)
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{
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u32 *arg = data;
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
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imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
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break;
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case IMX_MU_TYPE_TXDB:
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imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
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tasklet_schedule(&cp->txdb_tasklet);
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break;
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default:
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dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
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return -EINVAL;
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}
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return 0;
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}
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static int imx_mu_generic_rx(struct imx_mu_priv *priv,
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struct imx_mu_con_priv *cp)
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{
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u32 dat;
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dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
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mbox_chan_received_data(cp->chan, (void *)&dat);
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return 0;
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}
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static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
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struct imx_mu_con_priv *cp)
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{
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imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
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priv->dcfg->xSR[IMX_MU_GSR]);
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mbox_chan_received_data(cp->chan, NULL);
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return 0;
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}
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static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
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{
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u32 *arg = data;
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int i, ret;
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u32 xsr;
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u32 size, max_size, num_tr;
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if (priv->dcfg->type & IMX_MU_V2_S4) {
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size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
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max_size = sizeof(struct imx_s4_rpc_msg_max);
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num_tr = 8;
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} else {
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size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
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max_size = sizeof(struct imx_sc_rpc_msg_max);
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num_tr = 4;
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}
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switch (cp->type) {
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case IMX_MU_TYPE_TX:
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/*
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* msg->hdr.size specifies the number of u32 words while
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* sizeof yields bytes.
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*/
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if (size > max_size / 4) {
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/*
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* The real message size can be different to
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* struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size
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*/
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dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2);
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return -EINVAL;
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}
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for (i = 0; i < num_tr && i < size; i++)
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imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
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for (; i < size; i++) {
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ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
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xsr,
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xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),
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0, 5 * USEC_PER_SEC);
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if (ret) {
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dev_err(priv->dev, "Send data index: %d timeout\n", i);
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return ret;
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}
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imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
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}
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imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
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break;
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default:
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dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
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return -EINVAL;
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}
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return 0;
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}
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static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
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{
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u32 *data;
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int i, ret;
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u32 xsr;
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u32 size, max_size;
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data = (u32 *)priv->msg;
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
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*data++ = imx_mu_read(priv, priv->dcfg->xRR);
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if (priv->dcfg->type & IMX_MU_V2_S4) {
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size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size;
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max_size = sizeof(struct imx_s4_rpc_msg_max);
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} else {
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size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size;
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max_size = sizeof(struct imx_sc_rpc_msg_max);
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}
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if (size > max_size / 4) {
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dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2);
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return -EINVAL;
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}
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for (i = 1; i < size; i++) {
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ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
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xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0,
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5 * USEC_PER_SEC);
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if (ret) {
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dev_err(priv->dev, "timeout read idx %d\n", i);
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return ret;
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}
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*data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
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}
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imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
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mbox_chan_received_data(cp->chan, (void *)priv->msg);
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return 0;
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}
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static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
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void *data)
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{
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struct imx_sc_rpc_msg_max *msg = data;
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u32 *arg = data;
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u32 byte_size;
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int err;
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int i;
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dev_dbg(priv->dev, "Sending message\n");
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switch (cp->type) {
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case IMX_MU_TYPE_TXDB:
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byte_size = msg->hdr.size * sizeof(u32);
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if (byte_size > sizeof(*msg)) {
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/*
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* The real message size can be different to
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* struct imx_sc_rpc_msg_max size
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*/
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dev_err(priv->dev,
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"Exceed max msg size (%zu) on TX, got: %i\n",
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sizeof(*msg), byte_size);
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return -EINVAL;
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}
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print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4,
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data, byte_size, false);
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/* Send first word */
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dev_dbg(priv->dev, "Sending header\n");
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imx_mu_write(priv, *arg++, priv->dcfg->xTR);
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/* Send signaling */
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dev_dbg(priv->dev, "Sending signaling\n");
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imx_mu_xcr_rmw(priv, IMX_MU_GCR,
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IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
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/* Send words to fill the mailbox */
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for (i = 1; i < 4 && i < msg->hdr.size; i++) {
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dev_dbg(priv->dev, "Sending word %d\n", i);
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imx_mu_write(priv, *arg++,
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priv->dcfg->xTR + (i % 4) * 4);
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}
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/* Send rest of message waiting for remote read */
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for (; i < msg->hdr.size; i++) {
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dev_dbg(priv->dev, "Sending word %d\n", i);
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err = imx_mu_tx_waiting_write(priv, *arg++, i);
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if (err) {
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dev_err(priv->dev, "Timeout tx %d\n", i);
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return err;
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}
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}
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/* Simulate hack for mbox framework */
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tasklet_schedule(&cp->txdb_tasklet);
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break;
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default:
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dev_warn_ratelimited(priv->dev,
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"Send data on wrong channel type: %d\n",
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cp->type);
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return -EINVAL;
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}
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return 0;
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}
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static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
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{
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struct imx_sc_rpc_msg_max msg;
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u32 *data = (u32 *)&msg;
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u32 byte_size;
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int err = 0;
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int i;
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dev_dbg(priv->dev, "Receiving message\n");
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/* Read header */
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dev_dbg(priv->dev, "Receiving header\n");
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*data++ = imx_mu_read(priv, priv->dcfg->xRR);
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byte_size = msg.hdr.size * sizeof(u32);
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if (byte_size > sizeof(msg)) {
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dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n",
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sizeof(msg), byte_size);
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err = -EINVAL;
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goto error;
|
|
}
|
|
|
|
/* Read message waiting they are written */
|
|
for (i = 1; i < msg.hdr.size; i++) {
|
|
dev_dbg(priv->dev, "Receiving word %d\n", i);
|
|
err = imx_mu_rx_waiting_read(priv, data++, i);
|
|
if (err) {
|
|
dev_err(priv->dev, "Timeout rx %d\n", i);
|
|
goto error;
|
|
}
|
|
}
|
|
|
|
/* Clear GIP */
|
|
imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
|
|
priv->dcfg->xSR[IMX_MU_GSR]);
|
|
|
|
print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4,
|
|
&msg, byte_size, false);
|
|
|
|
/* send data to client */
|
|
dev_dbg(priv->dev, "Sending message to client\n");
|
|
mbox_chan_received_data(cp->chan, (void *)&msg);
|
|
|
|
goto exit;
|
|
|
|
error:
|
|
mbox_chan_received_data(cp->chan, ERR_PTR(err));
|
|
|
|
exit:
|
|
return err;
|
|
}
|
|
|
|
static void imx_mu_txdb_tasklet(unsigned long data)
|
|
{
|
|
struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
|
|
|
|
mbox_chan_txdone(cp->chan, 0);
|
|
}
|
|
|
|
static irqreturn_t imx_mu_isr(int irq, void *p)
|
|
{
|
|
struct mbox_chan *chan = p;
|
|
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
|
|
struct imx_mu_con_priv *cp = chan->con_priv;
|
|
u32 val, ctrl;
|
|
|
|
switch (cp->type) {
|
|
case IMX_MU_TYPE_TX:
|
|
ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
|
|
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
|
|
val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
|
|
(ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
|
|
break;
|
|
case IMX_MU_TYPE_RX:
|
|
ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
|
|
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
|
|
val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
|
|
(ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
|
|
break;
|
|
case IMX_MU_TYPE_RXDB:
|
|
ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);
|
|
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
|
|
val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
|
|
(ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
|
|
break;
|
|
case IMX_MU_TYPE_RST:
|
|
return IRQ_NONE;
|
|
default:
|
|
dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",
|
|
cp->type);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
if (!val)
|
|
return IRQ_NONE;
|
|
|
|
if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
|
|
(cp->type == IMX_MU_TYPE_TX)) {
|
|
imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
|
|
mbox_chan_txdone(chan, 0);
|
|
} else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
|
|
(cp->type == IMX_MU_TYPE_RX)) {
|
|
priv->dcfg->rx(priv, cp);
|
|
} else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
|
|
(cp->type == IMX_MU_TYPE_RXDB)) {
|
|
priv->dcfg->rxdb(priv, cp);
|
|
} else {
|
|
dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
if (priv->suspend)
|
|
pm_system_wakeup();
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int imx_mu_send_data(struct mbox_chan *chan, void *data)
|
|
{
|
|
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
|
|
struct imx_mu_con_priv *cp = chan->con_priv;
|
|
|
|
return priv->dcfg->tx(priv, cp, data);
|
|
}
|
|
|
|
static int imx_mu_startup(struct mbox_chan *chan)
|
|
{
|
|
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
|
|
struct imx_mu_con_priv *cp = chan->con_priv;
|
|
unsigned long irq_flag = 0;
|
|
int ret;
|
|
|
|
pm_runtime_get_sync(priv->dev);
|
|
if (cp->type == IMX_MU_TYPE_TXDB) {
|
|
/* Tx doorbell don't have ACK support */
|
|
tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
|
|
(unsigned long)cp);
|
|
return 0;
|
|
}
|
|
|
|
/* IPC MU should be with IRQF_NO_SUSPEND set */
|
|
if (!priv->dev->pm_domain)
|
|
irq_flag |= IRQF_NO_SUSPEND;
|
|
|
|
if (!(priv->dcfg->type & IMX_MU_V2_IRQ))
|
|
irq_flag |= IRQF_SHARED;
|
|
|
|
ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan);
|
|
if (ret) {
|
|
dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]);
|
|
return ret;
|
|
}
|
|
|
|
switch (cp->type) {
|
|
case IMX_MU_TYPE_RX:
|
|
imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
|
|
break;
|
|
case IMX_MU_TYPE_RXDB:
|
|
imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void imx_mu_shutdown(struct mbox_chan *chan)
|
|
{
|
|
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
|
|
struct imx_mu_con_priv *cp = chan->con_priv;
|
|
int ret;
|
|
u32 sr;
|
|
|
|
if (cp->type == IMX_MU_TYPE_TXDB) {
|
|
tasklet_kill(&cp->txdb_tasklet);
|
|
pm_runtime_put_sync(priv->dev);
|
|
return;
|
|
}
|
|
|
|
switch (cp->type) {
|
|
case IMX_MU_TYPE_TX:
|
|
imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
|
|
break;
|
|
case IMX_MU_TYPE_RX:
|
|
imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
|
|
break;
|
|
case IMX_MU_TYPE_RXDB:
|
|
imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
|
|
break;
|
|
case IMX_MU_TYPE_RST:
|
|
imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);
|
|
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr,
|
|
!(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5);
|
|
if (ret)
|
|
dev_warn(priv->dev, "RST channel timeout\n");
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
free_irq(priv->irq[cp->type], chan);
|
|
pm_runtime_put_sync(priv->dev);
|
|
}
|
|
|
|
static const struct mbox_chan_ops imx_mu_ops = {
|
|
.send_data = imx_mu_send_data,
|
|
.startup = imx_mu_startup,
|
|
.shutdown = imx_mu_shutdown,
|
|
};
|
|
|
|
static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox,
|
|
const struct of_phandle_args *sp)
|
|
{
|
|
u32 type, idx, chan;
|
|
|
|
if (sp->args_count != 2) {
|
|
dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
type = sp->args[0]; /* channel type */
|
|
idx = sp->args[1]; /* index */
|
|
|
|
switch (type) {
|
|
case IMX_MU_TYPE_TX:
|
|
case IMX_MU_TYPE_RX:
|
|
if (idx != 0)
|
|
dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
|
|
chan = type;
|
|
break;
|
|
case IMX_MU_TYPE_RXDB:
|
|
chan = 2 + idx;
|
|
break;
|
|
default:
|
|
dev_err(mbox->dev, "Invalid chan type: %d\n", type);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
if (chan >= mbox->num_chans) {
|
|
dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
return &mbox->chans[chan];
|
|
}
|
|
|
|
static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
|
|
const struct of_phandle_args *sp)
|
|
{
|
|
u32 type, idx, chan;
|
|
|
|
if (sp->args_count != 2) {
|
|
dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
type = sp->args[0]; /* channel type */
|
|
idx = sp->args[1]; /* index */
|
|
chan = type * 4 + idx;
|
|
|
|
if (chan >= mbox->num_chans) {
|
|
dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
return &mbox->chans[chan];
|
|
}
|
|
|
|
static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
|
|
const struct of_phandle_args *sp)
|
|
{
|
|
u32 type;
|
|
|
|
if (sp->args_count < 1) {
|
|
dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
type = sp->args[0]; /* channel type */
|
|
|
|
/* Only supports TXDB and RXDB */
|
|
if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) {
|
|
dev_err(mbox->dev, "Invalid type: %d\n", type);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
return imx_mu_xlate(mbox, sp);
|
|
}
|
|
|
|
static void imx_mu_init_generic(struct imx_mu_priv *priv)
|
|
{
|
|
unsigned int i;
|
|
unsigned int val;
|
|
|
|
for (i = 0; i < IMX_MU_CHANS; i++) {
|
|
struct imx_mu_con_priv *cp = &priv->con_priv[i];
|
|
|
|
cp->idx = i % 4;
|
|
cp->type = i >> 2;
|
|
cp->chan = &priv->mbox_chans[i];
|
|
priv->mbox_chans[i].con_priv = cp;
|
|
snprintf(cp->irq_desc, sizeof(cp->irq_desc),
|
|
"imx_mu_chan[%i-%i]", cp->type, cp->idx);
|
|
}
|
|
|
|
priv->mbox.num_chans = IMX_MU_CHANS;
|
|
priv->mbox.of_xlate = imx_mu_xlate;
|
|
|
|
if (priv->side_b)
|
|
return;
|
|
|
|
/* Set default MU configuration */
|
|
for (i = 0; i < IMX_MU_xCR_MAX; i++)
|
|
imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
|
|
|
|
/* Clear any pending GIP */
|
|
val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
|
|
imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);
|
|
|
|
/* Clear any pending RSR */
|
|
for (i = 0; i < IMX_MU_NUM_RR; i++)
|
|
imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
|
|
}
|
|
|
|
static void imx_mu_init_specific(struct imx_mu_priv *priv)
|
|
{
|
|
unsigned int i;
|
|
int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
|
|
|
|
for (i = 0; i < num_chans; i++) {
|
|
struct imx_mu_con_priv *cp = &priv->con_priv[i];
|
|
|
|
cp->idx = i < 2 ? 0 : i - 2;
|
|
cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
|
|
cp->chan = &priv->mbox_chans[i];
|
|
priv->mbox_chans[i].con_priv = cp;
|
|
snprintf(cp->irq_desc, sizeof(cp->irq_desc),
|
|
"imx_mu_chan[%i-%i]", cp->type, cp->idx);
|
|
}
|
|
|
|
priv->mbox.num_chans = num_chans;
|
|
priv->mbox.of_xlate = imx_mu_specific_xlate;
|
|
|
|
/* Set default MU configuration */
|
|
for (i = 0; i < IMX_MU_xCR_MAX; i++)
|
|
imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
|
|
}
|
|
|
|
static void imx_mu_init_seco(struct imx_mu_priv *priv)
|
|
{
|
|
imx_mu_init_generic(priv);
|
|
priv->mbox.of_xlate = imx_mu_seco_xlate;
|
|
}
|
|
|
|
static int imx_mu_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
struct imx_mu_priv *priv;
|
|
const struct imx_mu_dcfg *dcfg;
|
|
int i, ret;
|
|
u32 size;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->dev = dev;
|
|
|
|
priv->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(priv->base))
|
|
return PTR_ERR(priv->base);
|
|
|
|
dcfg = of_device_get_match_data(dev);
|
|
if (!dcfg)
|
|
return -EINVAL;
|
|
priv->dcfg = dcfg;
|
|
if (priv->dcfg->type & IMX_MU_V2_IRQ) {
|
|
priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx");
|
|
if (priv->irq[IMX_MU_TYPE_TX] < 0)
|
|
return priv->irq[IMX_MU_TYPE_TX];
|
|
priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx");
|
|
if (priv->irq[IMX_MU_TYPE_RX] < 0)
|
|
return priv->irq[IMX_MU_TYPE_RX];
|
|
} else {
|
|
ret = platform_get_irq(pdev, 0);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
for (i = 0; i < IMX_MU_CHANS; i++)
|
|
priv->irq[i] = ret;
|
|
}
|
|
|
|
if (priv->dcfg->type & IMX_MU_V2_S4)
|
|
size = sizeof(struct imx_s4_rpc_msg_max);
|
|
else
|
|
size = sizeof(struct imx_sc_rpc_msg_max);
|
|
|
|
priv->msg = devm_kzalloc(dev, size, GFP_KERNEL);
|
|
if (!priv->msg)
|
|
return -ENOMEM;
|
|
|
|
priv->clk = devm_clk_get(dev, NULL);
|
|
if (IS_ERR(priv->clk)) {
|
|
if (PTR_ERR(priv->clk) != -ENOENT)
|
|
return PTR_ERR(priv->clk);
|
|
|
|
priv->clk = NULL;
|
|
}
|
|
|
|
ret = clk_prepare_enable(priv->clk);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to enable clock\n");
|
|
return ret;
|
|
}
|
|
|
|
priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
|
|
|
|
priv->dcfg->init(priv);
|
|
|
|
spin_lock_init(&priv->xcr_lock);
|
|
|
|
priv->mbox.dev = dev;
|
|
priv->mbox.ops = &imx_mu_ops;
|
|
priv->mbox.chans = priv->mbox_chans;
|
|
priv->mbox.txdone_irq = true;
|
|
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
ret = devm_mbox_controller_register(dev, &priv->mbox);
|
|
if (ret) {
|
|
clk_disable_unprepare(priv->clk);
|
|
return ret;
|
|
}
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
ret = pm_runtime_resume_and_get(dev);
|
|
if (ret < 0)
|
|
goto disable_runtime_pm;
|
|
|
|
ret = pm_runtime_put_sync(dev);
|
|
if (ret < 0)
|
|
goto disable_runtime_pm;
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
return 0;
|
|
|
|
disable_runtime_pm:
|
|
pm_runtime_disable(dev);
|
|
clk_disable_unprepare(priv->clk);
|
|
return ret;
|
|
}
|
|
|
|
static int imx_mu_remove(struct platform_device *pdev)
|
|
{
|
|
struct imx_mu_priv *priv = platform_get_drvdata(pdev);
|
|
|
|
pm_runtime_disable(priv->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
|
|
.tx = imx_mu_generic_tx,
|
|
.rx = imx_mu_generic_rx,
|
|
.rxdb = imx_mu_generic_rxdb,
|
|
.init = imx_mu_init_generic,
|
|
.xTR = 0x0,
|
|
.xRR = 0x10,
|
|
.xSR = {0x20, 0x20, 0x20, 0x20},
|
|
.xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
|
|
};
|
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
|
|
.tx = imx_mu_generic_tx,
|
|
.rx = imx_mu_generic_rx,
|
|
.rxdb = imx_mu_generic_rxdb,
|
|
.init = imx_mu_init_generic,
|
|
.xTR = 0x20,
|
|
.xRR = 0x40,
|
|
.xSR = {0x60, 0x60, 0x60, 0x60},
|
|
.xCR = {0x64, 0x64, 0x64, 0x64, 0x64},
|
|
};
|
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
|
|
.tx = imx_mu_generic_tx,
|
|
.rx = imx_mu_generic_rx,
|
|
.rxdb = imx_mu_generic_rxdb,
|
|
.init = imx_mu_init_generic,
|
|
.type = IMX_MU_V2,
|
|
.xTR = 0x200,
|
|
.xRR = 0x280,
|
|
.xSR = {0xC, 0x118, 0x124, 0x12C},
|
|
.xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
|
|
};
|
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
|
|
.tx = imx_mu_specific_tx,
|
|
.rx = imx_mu_specific_rx,
|
|
.init = imx_mu_init_specific,
|
|
.type = IMX_MU_V2 | IMX_MU_V2_S4,
|
|
.xTR = 0x200,
|
|
.xRR = 0x280,
|
|
.xSR = {0xC, 0x118, 0x124, 0x12C},
|
|
.xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
|
|
};
|
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
|
|
.tx = imx_mu_specific_tx,
|
|
.rx = imx_mu_specific_rx,
|
|
.init = imx_mu_init_specific,
|
|
.type = IMX_MU_V2 | IMX_MU_V2_S4 | IMX_MU_V2_IRQ,
|
|
.xTR = 0x200,
|
|
.xRR = 0x280,
|
|
.xSR = {0xC, 0x118, 0x124, 0x12C},
|
|
.xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
|
|
};
|
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
|
|
.tx = imx_mu_specific_tx,
|
|
.rx = imx_mu_specific_rx,
|
|
.init = imx_mu_init_specific,
|
|
.rxdb = imx_mu_generic_rxdb,
|
|
.xTR = 0x0,
|
|
.xRR = 0x10,
|
|
.xSR = {0x20, 0x20, 0x20, 0x20},
|
|
.xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
|
|
};
|
|
|
|
static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
|
|
.tx = imx_mu_seco_tx,
|
|
.rx = imx_mu_generic_rx,
|
|
.rxdb = imx_mu_seco_rxdb,
|
|
.init = imx_mu_init_seco,
|
|
.xTR = 0x0,
|
|
.xRR = 0x10,
|
|
.xSR = {0x20, 0x20, 0x20, 0x20},
|
|
.xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
|
|
};
|
|
|
|
static const struct of_device_id imx_mu_dt_ids[] = {
|
|
{ .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
|
|
{ .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
|
|
{ .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
|
|
{ .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
|
|
{ .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
|
|
{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
|
|
{ .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
|
|
|
|
static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
|
|
{
|
|
struct imx_mu_priv *priv = dev_get_drvdata(dev);
|
|
int i;
|
|
|
|
if (!priv->clk) {
|
|
for (i = 0; i < IMX_MU_xCR_MAX; i++)
|
|
priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
|
|
}
|
|
|
|
priv->suspend = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
|
|
{
|
|
struct imx_mu_priv *priv = dev_get_drvdata(dev);
|
|
int i;
|
|
|
|
/*
|
|
* ONLY restore MU when context lost, the TIE could
|
|
* be set during noirq resume as there is MU data
|
|
* communication going on, and restore the saved
|
|
* value will overwrite the TIE and cause MU data
|
|
* send failed, may lead to system freeze. This issue
|
|
* is observed by testing freeze mode suspend.
|
|
*/
|
|
if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) {
|
|
for (i = 0; i < IMX_MU_xCR_MAX; i++)
|
|
imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);
|
|
}
|
|
|
|
priv->suspend = false;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
|
|
{
|
|
struct imx_mu_priv *priv = dev_get_drvdata(dev);
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
|
|
{
|
|
struct imx_mu_priv *priv = dev_get_drvdata(dev);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(priv->clk);
|
|
if (ret)
|
|
dev_err(dev, "failed to enable clock\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dev_pm_ops imx_mu_pm_ops = {
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
|
|
imx_mu_resume_noirq)
|
|
SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
|
|
imx_mu_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct platform_driver imx_mu_driver = {
|
|
.probe = imx_mu_probe,
|
|
.remove = imx_mu_remove,
|
|
.driver = {
|
|
.name = "imx_mu",
|
|
.of_match_table = imx_mu_dt_ids,
|
|
.pm = &imx_mu_pm_ops,
|
|
},
|
|
};
|
|
module_platform_driver(imx_mu_driver);
|
|
|
|
MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
|
|
MODULE_DESCRIPTION("Message Unit driver for i.MX");
|
|
MODULE_LICENSE("GPL v2");
|