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e156e4d2e4
Advertise the maximum offset the .adjphase callback is capable of supporting in nanoseconds for IDT devices. Refactor the negation of the offset stored in the register to be after the boundary check of the offset value rather than before. Boundary check based on the intended value rather than its device-specific representation. Depend on ptp_clock_adjtime for handling out-of-range offsets. ptp_clock_adjtime returns -ERANGE instead of clamping out-of-range offsets. Cc: Richard Cochran <richardcochran@gmail.com> Cc: Min Li <min.li.xe@renesas.com> Signed-off-by: Rahul Rameshbabu <rrameshbabu@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* PTP hardware clock driver for the IDT 82P33XXX family of clocks.
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*
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* Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
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*/
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#ifndef PTP_IDT82P33_H
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#define PTP_IDT82P33_H
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#include <linux/ktime.h>
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#include <linux/mfd/idt82p33_reg.h>
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#include <linux/regmap.h>
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#define FW_FILENAME "idt82p33xxx.bin"
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#define MAX_PHC_PLL (2)
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#define MAX_TRIG_CLK (3)
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#define MAX_PER_OUT (11)
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#define TOD_BYTE_COUNT (10)
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#define DCO_MAX_PPB (92000)
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#define MAX_MEASURMENT_COUNT (5)
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#define SNAP_THRESHOLD_NS (10000)
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#define IMMEDIATE_SNAP_THRESHOLD_NS (50000)
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#define DDCO_THRESHOLD_NS (5)
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#define IDT82P33_MAX_WRITE_COUNT (512)
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#define PLLMASK_ADDR_HI 0xFF
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#define PLLMASK_ADDR_LO 0xA5
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#define PLL0_OUTMASK_ADDR_HI 0xFF
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#define PLL0_OUTMASK_ADDR_LO 0xB0
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#define PLL1_OUTMASK_ADDR_HI 0xFF
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#define PLL1_OUTMASK_ADDR_LO 0xB2
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#define PLL2_OUTMASK_ADDR_HI 0xFF
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#define PLL2_OUTMASK_ADDR_LO 0xB4
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#define PLL3_OUTMASK_ADDR_HI 0xFF
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#define PLL3_OUTMASK_ADDR_LO 0xB6
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#define DEFAULT_PLL_MASK (0x01)
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#define DEFAULT_OUTPUT_MASK_PLL0 (0xc0)
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#define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0
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/**
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* @brief Maximum absolute value for write phase offset in nanoseconds
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*/
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#define WRITE_PHASE_OFFSET_LIMIT (20000l)
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/** @brief Phase offset resolution
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*
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* DPLL phase offset = 10^15 fs / ( System Clock * 2^13)
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* = 10^15 fs / ( 1638400000 * 2^23)
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* = 74.5058059692382 fs
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*/
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#define IDT_T0DPLL_PHASE_RESOL 74506
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/* PTP Hardware Clock interface */
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struct idt82p33_channel {
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struct ptp_clock_info caps;
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struct ptp_clock *ptp_clock;
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struct idt82p33 *idt82p33;
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enum pll_mode pll_mode;
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/* Workaround for TOD-to-output alignment issue */
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struct delayed_work adjtime_work;
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s32 current_freq;
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/* double dco mode */
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bool ddco;
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u8 output_mask;
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/* last input trigger for extts */
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u8 tod_trigger;
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bool discard_next_extts;
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u8 plln;
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/* remember last tod_sts for extts */
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u8 extts_tod_sts[TOD_BYTE_COUNT];
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u16 dpll_tod_cnfg;
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u16 dpll_tod_trigger;
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u16 dpll_tod_sts;
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u16 dpll_mode_cnfg;
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u16 dpll_freq_cnfg;
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u16 dpll_phase_cnfg;
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u16 dpll_sync_cnfg;
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u16 dpll_input_mode_cnfg;
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};
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struct idt82p33 {
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struct idt82p33_channel channel[MAX_PHC_PLL];
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struct device *dev;
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u8 pll_mask;
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/* Polls for external time stamps */
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u8 extts_mask;
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bool extts_single_shot;
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struct delayed_work extts_work;
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/* Remember the ptp channel to report extts */
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struct idt82p33_channel *event_channel[MAX_PHC_PLL];
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/* Mutex to protect operations from being interrupted */
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struct mutex *lock;
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struct regmap *regmap;
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struct device *mfd;
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/* Overhead calculation for adjtime */
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ktime_t start_time;
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int calculate_overhead_flag;
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s64 tod_write_overhead_ns;
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};
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/* firmware interface */
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struct idt82p33_fwrc {
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u8 hiaddr;
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u8 loaddr;
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u8 value;
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u8 reserved;
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} __packed;
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#endif /* PTP_IDT82P33_H */
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