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![Thomas Kastner](/assets/img/avatar_default.png)
This patch adds the 'advantech_ec_wdt' kernel module which provides WDT support for Advantech platforms with ITE based Embedded Controller. Signed-off-by: Thomas Kastner <thomas.kastner@advantech.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Thomas Kastner <thomas.kastner@advantech.com> Link: https://lore.kernel.org/r/Y0+pl/26e3pcEUPk@EIS-S230 Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
205 lines
5.1 KiB
C
205 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Advantech Embedded Controller Watchdog Driver
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*
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* This driver supports Advantech products with ITE based Embedded Controller.
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* It does not support Advantech products with other ECs or without EC.
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*
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* Copyright (C) 2022 Advantech Europe B.V.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/isa.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/watchdog.h>
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#define DRIVER_NAME "advantech_ec_wdt"
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/* EC IO region */
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#define EC_BASE_ADDR 0x299
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#define EC_ADDR_EXTENT 2
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/* EC minimum IO access delay in ms */
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#define EC_MIN_DELAY 10
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/* EC interface definitions */
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#define EC_ADDR_CMD (EC_BASE_ADDR + 1)
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#define EC_ADDR_DATA EC_BASE_ADDR
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#define EC_CMD_EC_PROBE 0x30
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#define EC_CMD_COMM 0x89
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#define EC_CMD_WDT_START 0x28
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#define EC_CMD_WDT_STOP 0x29
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#define EC_CMD_WDT_RESET 0x2A
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#define EC_DAT_EN_DLY_H 0x58
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#define EC_DAT_EN_DLY_L 0x59
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#define EC_DAT_RST_DLY_H 0x5E
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#define EC_DAT_RST_DLY_L 0x5F
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#define EC_MAGIC 0x95
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/* module parameters */
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#define MIN_TIME 1
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#define MAX_TIME 6000 /* 100 minutes */
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#define DEFAULT_TIME 60
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static unsigned int timeout;
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static ktime_t ec_timestamp;
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module_param(timeout, uint, 0);
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MODULE_PARM_DESC(timeout,
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"Default Watchdog timer setting (" __MODULE_STRING(DEFAULT_TIME) "s). The range is from " __MODULE_STRING(MIN_TIME) " to " __MODULE_STRING(MAX_TIME) ".");
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static void adv_ec_wdt_timing_gate(void)
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{
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ktime_t time_cur, time_delta;
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/* ensure minimum delay between IO accesses*/
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time_cur = ktime_get();
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time_delta = ktime_to_ms(ktime_sub(time_cur, ec_timestamp));
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if (time_delta < EC_MIN_DELAY) {
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time_delta = EC_MIN_DELAY - time_delta;
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usleep_range(time_delta * 1000, (time_delta + 1) * 1000);
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}
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ec_timestamp = ktime_get();
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}
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static void adv_ec_wdt_outb(unsigned char value, unsigned short port)
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{
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adv_ec_wdt_timing_gate();
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outb(value, port);
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}
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static unsigned char adv_ec_wdt_inb(unsigned short port)
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{
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adv_ec_wdt_timing_gate();
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return inb(port);
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}
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static int adv_ec_wdt_ping(struct watchdog_device *wdd)
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{
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adv_ec_wdt_outb(EC_CMD_WDT_RESET, EC_ADDR_CMD);
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return 0;
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}
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static int adv_ec_wdt_set_timeout(struct watchdog_device *wdd, unsigned int t)
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{
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unsigned int val;
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/* scale time to EC 100 ms base */
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val = t * 10;
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/* reset enable delay, just in case it was set by BIOS etc. */
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adv_ec_wdt_outb(EC_CMD_COMM, EC_ADDR_CMD);
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adv_ec_wdt_outb(EC_DAT_EN_DLY_H, EC_ADDR_DATA);
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adv_ec_wdt_outb(0, EC_ADDR_DATA);
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adv_ec_wdt_outb(EC_CMD_COMM, EC_ADDR_CMD);
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adv_ec_wdt_outb(EC_DAT_EN_DLY_L, EC_ADDR_DATA);
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adv_ec_wdt_outb(0, EC_ADDR_DATA);
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/* set reset delay */
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adv_ec_wdt_outb(EC_CMD_COMM, EC_ADDR_CMD);
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adv_ec_wdt_outb(EC_DAT_RST_DLY_H, EC_ADDR_DATA);
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adv_ec_wdt_outb(val >> 8, EC_ADDR_DATA);
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adv_ec_wdt_outb(EC_CMD_COMM, EC_ADDR_CMD);
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adv_ec_wdt_outb(EC_DAT_RST_DLY_L, EC_ADDR_DATA);
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adv_ec_wdt_outb(val & 0xFF, EC_ADDR_DATA);
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wdd->timeout = t;
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return 0;
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}
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static int adv_ec_wdt_start(struct watchdog_device *wdd)
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{
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adv_ec_wdt_set_timeout(wdd, wdd->timeout);
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adv_ec_wdt_outb(EC_CMD_WDT_START, EC_ADDR_CMD);
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return 0;
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}
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static int adv_ec_wdt_stop(struct watchdog_device *wdd)
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{
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adv_ec_wdt_outb(EC_CMD_WDT_STOP, EC_ADDR_CMD);
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return 0;
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}
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static const struct watchdog_info adv_ec_wdt_info = {
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.identity = DRIVER_NAME,
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.options = WDIOF_SETTIMEOUT |
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WDIOF_MAGICCLOSE |
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WDIOF_KEEPALIVEPING,
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};
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static const struct watchdog_ops adv_ec_wdt_ops = {
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.owner = THIS_MODULE,
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.start = adv_ec_wdt_start,
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.stop = adv_ec_wdt_stop,
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.ping = adv_ec_wdt_ping,
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.set_timeout = adv_ec_wdt_set_timeout,
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};
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static struct watchdog_device adv_ec_wdt_dev = {
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.info = &adv_ec_wdt_info,
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.ops = &adv_ec_wdt_ops,
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.min_timeout = MIN_TIME,
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.max_timeout = MAX_TIME,
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.timeout = DEFAULT_TIME,
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};
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static int adv_ec_wdt_probe(struct device *dev, unsigned int id)
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{
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if (!devm_request_region(dev, EC_BASE_ADDR, EC_ADDR_EXTENT, dev_name(dev))) {
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dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
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EC_BASE_ADDR, EC_BASE_ADDR + EC_ADDR_EXTENT);
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return -EBUSY;
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}
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watchdog_init_timeout(&adv_ec_wdt_dev, timeout, dev);
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watchdog_stop_on_reboot(&adv_ec_wdt_dev);
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watchdog_stop_on_unregister(&adv_ec_wdt_dev);
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return devm_watchdog_register_device(dev, &adv_ec_wdt_dev);
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}
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static struct isa_driver adv_ec_wdt_driver = {
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.probe = adv_ec_wdt_probe,
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.driver = {
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.name = DRIVER_NAME,
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},
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};
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static int __init adv_ec_wdt_init(void)
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{
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unsigned int val;
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/* quick probe for EC */
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if (!request_region(EC_BASE_ADDR, EC_ADDR_EXTENT, DRIVER_NAME))
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return -EBUSY;
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adv_ec_wdt_outb(EC_CMD_EC_PROBE, EC_ADDR_CMD);
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val = adv_ec_wdt_inb(EC_ADDR_DATA);
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release_region(EC_BASE_ADDR, EC_ADDR_EXTENT);
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if (val != EC_MAGIC)
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return -ENODEV;
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return isa_register_driver(&adv_ec_wdt_driver, 1);
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}
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static void __exit adv_ec_wdt_exit(void)
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{
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isa_unregister_driver(&adv_ec_wdt_driver);
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}
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module_init(adv_ec_wdt_init);
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module_exit(adv_ec_wdt_exit);
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MODULE_AUTHOR("Thomas Kastner <thomas.kastner@advantech.com>");
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MODULE_DESCRIPTION("Advantech Embedded Controller Watchdog Device Driver");
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MODULE_LICENSE("GPL");
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MODULE_VERSION("20221019");
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MODULE_ALIAS("isa:" DRIVER_NAME);
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