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On the Nuvoton WPCM450 SoC, with its upcoming clock driver, peripheral clocks are individually gated and ungated. Therefore, the watchdog driver must be able to ungate the watchdog clock. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20220610072141.347795-3-j.neuschaefer@gmx.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
266 lines
5.9 KiB
C
266 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018 Nuvoton Technology corporation.
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// Copyright (c) 2018 IBM Corp.
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/watchdog.h>
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#define NPCM_WTCR 0x1C
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#define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */
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#define NPCM_WTE BIT(7) /* Enable */
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#define NPCM_WTIE BIT(6) /* Enable irq */
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#define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */
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#define NPCM_WTIF BIT(3) /* Interrupt flag*/
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#define NPCM_WTRF BIT(2) /* Reset flag */
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#define NPCM_WTRE BIT(1) /* Reset enable */
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#define NPCM_WTR BIT(0) /* Reset counter */
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/*
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* Watchdog timeouts
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*
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* 170 msec: WTCLK=01 WTIS=00 VAL= 0x400
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* 670 msec: WTCLK=01 WTIS=01 VAL= 0x410
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* 1360 msec: WTCLK=10 WTIS=00 VAL= 0x800
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* 2700 msec: WTCLK=01 WTIS=10 VAL= 0x420
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* 5360 msec: WTCLK=10 WTIS=01 VAL= 0x810
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* 10700 msec: WTCLK=01 WTIS=11 VAL= 0x430
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* 21600 msec: WTCLK=10 WTIS=10 VAL= 0x820
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* 43000 msec: WTCLK=11 WTIS=00 VAL= 0xC00
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* 85600 msec: WTCLK=10 WTIS=11 VAL= 0x830
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* 172000 msec: WTCLK=11 WTIS=01 VAL= 0xC10
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* 687000 msec: WTCLK=11 WTIS=10 VAL= 0xC20
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* 2750000 msec: WTCLK=11 WTIS=11 VAL= 0xC30
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*/
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struct npcm_wdt {
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struct watchdog_device wdd;
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void __iomem *reg;
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struct clk *clk;
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};
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static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd)
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{
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return container_of(wdd, struct npcm_wdt, wdd);
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}
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static int npcm_wdt_ping(struct watchdog_device *wdd)
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{
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struct npcm_wdt *wdt = to_npcm_wdt(wdd);
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u32 val;
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val = readl(wdt->reg);
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writel(val | NPCM_WTR, wdt->reg);
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return 0;
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}
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static int npcm_wdt_start(struct watchdog_device *wdd)
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{
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struct npcm_wdt *wdt = to_npcm_wdt(wdd);
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u32 val;
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if (wdt->clk)
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clk_prepare_enable(wdt->clk);
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if (wdd->timeout < 2)
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val = 0x800;
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else if (wdd->timeout < 3)
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val = 0x420;
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else if (wdd->timeout < 6)
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val = 0x810;
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else if (wdd->timeout < 11)
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val = 0x430;
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else if (wdd->timeout < 22)
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val = 0x820;
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else if (wdd->timeout < 44)
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val = 0xC00;
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else if (wdd->timeout < 87)
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val = 0x830;
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else if (wdd->timeout < 173)
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val = 0xC10;
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else if (wdd->timeout < 688)
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val = 0xC20;
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else
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val = 0xC30;
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val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE;
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writel(val, wdt->reg);
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return 0;
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}
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static int npcm_wdt_stop(struct watchdog_device *wdd)
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{
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struct npcm_wdt *wdt = to_npcm_wdt(wdd);
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writel(0, wdt->reg);
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if (wdt->clk)
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clk_disable_unprepare(wdt->clk);
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return 0;
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}
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static int npcm_wdt_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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if (timeout < 2)
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wdd->timeout = 1;
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else if (timeout < 3)
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wdd->timeout = 2;
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else if (timeout < 6)
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wdd->timeout = 5;
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else if (timeout < 11)
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wdd->timeout = 10;
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else if (timeout < 22)
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wdd->timeout = 21;
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else if (timeout < 44)
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wdd->timeout = 43;
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else if (timeout < 87)
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wdd->timeout = 86;
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else if (timeout < 173)
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wdd->timeout = 172;
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else if (timeout < 688)
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wdd->timeout = 687;
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else
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wdd->timeout = 2750;
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if (watchdog_active(wdd))
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npcm_wdt_start(wdd);
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return 0;
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}
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static irqreturn_t npcm_wdt_interrupt(int irq, void *data)
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{
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struct npcm_wdt *wdt = data;
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watchdog_notify_pretimeout(&wdt->wdd);
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return IRQ_HANDLED;
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}
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static int npcm_wdt_restart(struct watchdog_device *wdd,
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unsigned long action, void *data)
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{
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struct npcm_wdt *wdt = to_npcm_wdt(wdd);
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/* For reset, we start the WDT clock and leave it running. */
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if (wdt->clk)
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clk_prepare_enable(wdt->clk);
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writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, wdt->reg);
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udelay(1000);
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return 0;
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}
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static bool npcm_is_running(struct watchdog_device *wdd)
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{
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struct npcm_wdt *wdt = to_npcm_wdt(wdd);
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return readl(wdt->reg) & NPCM_WTE;
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}
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static const struct watchdog_info npcm_wdt_info = {
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.identity = KBUILD_MODNAME,
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.options = WDIOF_SETTIMEOUT
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| WDIOF_KEEPALIVEPING
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| WDIOF_MAGICCLOSE,
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};
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static const struct watchdog_ops npcm_wdt_ops = {
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.owner = THIS_MODULE,
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.start = npcm_wdt_start,
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.stop = npcm_wdt_stop,
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.ping = npcm_wdt_ping,
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.set_timeout = npcm_wdt_set_timeout,
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.restart = npcm_wdt_restart,
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};
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static int npcm_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct npcm_wdt *wdt;
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int irq;
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int ret;
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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wdt->reg = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(wdt->reg))
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return PTR_ERR(wdt->reg);
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wdt->clk = devm_clk_get_optional(&pdev->dev, NULL);
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if (IS_ERR(wdt->clk))
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return PTR_ERR(wdt->clk);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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wdt->wdd.info = &npcm_wdt_info;
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wdt->wdd.ops = &npcm_wdt_ops;
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wdt->wdd.min_timeout = 1;
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wdt->wdd.max_timeout = 2750;
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wdt->wdd.parent = dev;
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wdt->wdd.timeout = 86;
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watchdog_init_timeout(&wdt->wdd, 0, dev);
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/* Ensure timeout is able to be represented by the hardware */
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npcm_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
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if (npcm_is_running(&wdt->wdd)) {
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/* Restart with the default or device-tree specified timeout */
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npcm_wdt_start(&wdt->wdd);
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set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
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}
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ret = devm_request_irq(dev, irq, npcm_wdt_interrupt, 0, "watchdog",
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wdt);
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if (ret)
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return ret;
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ret = devm_watchdog_register_device(dev, &wdt->wdd);
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if (ret)
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return ret;
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dev_info(dev, "NPCM watchdog driver enabled\n");
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return 0;
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}
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#ifdef CONFIG_OF
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static const struct of_device_id npcm_wdt_match[] = {
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{.compatible = "nuvoton,wpcm450-wdt"},
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{.compatible = "nuvoton,npcm750-wdt"},
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{},
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};
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MODULE_DEVICE_TABLE(of, npcm_wdt_match);
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#endif
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static struct platform_driver npcm_wdt_driver = {
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.probe = npcm_wdt_probe,
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.driver = {
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.name = "npcm-wdt",
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.of_match_table = of_match_ptr(npcm_wdt_match),
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},
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};
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module_platform_driver(npcm_wdt_driver);
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MODULE_AUTHOR("Joel Stanley");
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MODULE_DESCRIPTION("Watchdog driver for NPCM");
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MODULE_LICENSE("GPL v2");
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