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![Christophe JAILLET](/assets/img/avatar_default.png)
The devm_clk_get_enabled() helper: - calls devm_clk_get() - calls clk_prepare_enable() and registers what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code and avoids the need of a dedicated function used with devm_add_action_or_reset(). Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/7c2d5f3815949faf6d3a0237a7b5f272f00a7ae9.1672418969.git.christophe.jaillet@wanadoo.fr Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
341 lines
7.8 KiB
C
341 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*/
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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#include <linux/of_device.h>
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enum wdt_reg {
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WDT_RST,
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WDT_EN,
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WDT_STS,
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WDT_BARK_TIME,
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WDT_BITE_TIME,
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};
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#define QCOM_WDT_ENABLE BIT(0)
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static const u32 reg_offset_data_apcs_tmr[] = {
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[WDT_RST] = 0x38,
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[WDT_EN] = 0x40,
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[WDT_STS] = 0x44,
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[WDT_BARK_TIME] = 0x4C,
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[WDT_BITE_TIME] = 0x5C,
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};
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static const u32 reg_offset_data_kpss[] = {
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[WDT_RST] = 0x4,
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[WDT_EN] = 0x8,
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[WDT_STS] = 0xC,
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[WDT_BARK_TIME] = 0x10,
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[WDT_BITE_TIME] = 0x14,
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};
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struct qcom_wdt_match_data {
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const u32 *offset;
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bool pretimeout;
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};
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struct qcom_wdt {
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struct watchdog_device wdd;
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unsigned long rate;
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void __iomem *base;
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const u32 *layout;
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};
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static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg)
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{
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return wdt->base + wdt->layout[reg];
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}
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static inline
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struct qcom_wdt *to_qcom_wdt(struct watchdog_device *wdd)
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{
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return container_of(wdd, struct qcom_wdt, wdd);
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}
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static irqreturn_t qcom_wdt_isr(int irq, void *arg)
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{
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struct watchdog_device *wdd = arg;
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watchdog_notify_pretimeout(wdd);
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return IRQ_HANDLED;
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}
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static int qcom_wdt_start(struct watchdog_device *wdd)
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{
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struct qcom_wdt *wdt = to_qcom_wdt(wdd);
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unsigned int bark = wdd->timeout - wdd->pretimeout;
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writel(0, wdt_addr(wdt, WDT_EN));
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writel(1, wdt_addr(wdt, WDT_RST));
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writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
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writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
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writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
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return 0;
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}
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static int qcom_wdt_stop(struct watchdog_device *wdd)
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{
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struct qcom_wdt *wdt = to_qcom_wdt(wdd);
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writel(0, wdt_addr(wdt, WDT_EN));
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return 0;
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}
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static int qcom_wdt_ping(struct watchdog_device *wdd)
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{
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struct qcom_wdt *wdt = to_qcom_wdt(wdd);
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writel(1, wdt_addr(wdt, WDT_RST));
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return 0;
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}
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static int qcom_wdt_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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wdd->timeout = timeout;
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return qcom_wdt_start(wdd);
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}
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static int qcom_wdt_set_pretimeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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wdd->pretimeout = timeout;
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return qcom_wdt_start(wdd);
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}
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static int qcom_wdt_restart(struct watchdog_device *wdd, unsigned long action,
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void *data)
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{
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struct qcom_wdt *wdt = to_qcom_wdt(wdd);
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u32 timeout;
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/*
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* Trigger watchdog bite:
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* Setup BITE_TIME to be 128ms, and enable WDT.
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*/
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timeout = 128 * wdt->rate / 1000;
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writel(0, wdt_addr(wdt, WDT_EN));
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writel(1, wdt_addr(wdt, WDT_RST));
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writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
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writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
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writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN));
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/*
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* Actually make sure the above sequence hits hardware before sleeping.
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*/
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wmb();
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mdelay(150);
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return 0;
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}
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static int qcom_wdt_is_running(struct watchdog_device *wdd)
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{
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struct qcom_wdt *wdt = to_qcom_wdt(wdd);
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return (readl(wdt_addr(wdt, WDT_EN)) & QCOM_WDT_ENABLE);
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}
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static const struct watchdog_ops qcom_wdt_ops = {
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.start = qcom_wdt_start,
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.stop = qcom_wdt_stop,
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.ping = qcom_wdt_ping,
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.set_timeout = qcom_wdt_set_timeout,
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.set_pretimeout = qcom_wdt_set_pretimeout,
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.restart = qcom_wdt_restart,
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.owner = THIS_MODULE,
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};
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static const struct watchdog_info qcom_wdt_info = {
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.options = WDIOF_KEEPALIVEPING
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| WDIOF_MAGICCLOSE
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| WDIOF_SETTIMEOUT
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| WDIOF_CARDRESET,
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.identity = KBUILD_MODNAME,
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};
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static const struct watchdog_info qcom_wdt_pt_info = {
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.options = WDIOF_KEEPALIVEPING
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| WDIOF_MAGICCLOSE
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| WDIOF_SETTIMEOUT
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| WDIOF_PRETIMEOUT
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| WDIOF_CARDRESET,
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.identity = KBUILD_MODNAME,
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};
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static const struct qcom_wdt_match_data match_data_apcs_tmr = {
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.offset = reg_offset_data_apcs_tmr,
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.pretimeout = false,
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};
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static const struct qcom_wdt_match_data match_data_kpss = {
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.offset = reg_offset_data_kpss,
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.pretimeout = true,
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};
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static int qcom_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct qcom_wdt *wdt;
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struct resource *res;
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struct device_node *np = dev->of_node;
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const struct qcom_wdt_match_data *data;
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u32 percpu_offset;
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int irq, ret;
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struct clk *clk;
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data = of_device_get_match_data(dev);
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if (!data) {
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dev_err(dev, "Unsupported QCOM WDT module\n");
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return -ENODEV;
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}
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENOMEM;
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/* We use CPU0's DGT for the watchdog */
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if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
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percpu_offset = 0;
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res->start += percpu_offset;
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res->end += percpu_offset;
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wdt->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(wdt->base))
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return PTR_ERR(wdt->base);
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clk = devm_clk_get_enabled(dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to get input clock\n");
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return PTR_ERR(clk);
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}
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/*
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* We use the clock rate to calculate the max timeout, so ensure it's
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* not zero to avoid a divide-by-zero exception.
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*
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* WATCHDOG_CORE assumes units of seconds, if the WDT is clocked such
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* that it would bite before a second elapses it's usefulness is
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* limited. Bail if this is the case.
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*/
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wdt->rate = clk_get_rate(clk);
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if (wdt->rate == 0 ||
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wdt->rate > 0x10000000U) {
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dev_err(dev, "invalid clock rate\n");
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return -EINVAL;
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}
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/* check if there is pretimeout support */
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irq = platform_get_irq_optional(pdev, 0);
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if (data->pretimeout && irq > 0) {
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ret = devm_request_irq(dev, irq, qcom_wdt_isr, 0,
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"wdt_bark", &wdt->wdd);
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if (ret)
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return ret;
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wdt->wdd.info = &qcom_wdt_pt_info;
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wdt->wdd.pretimeout = 1;
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} else {
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if (irq == -EPROBE_DEFER)
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return -EPROBE_DEFER;
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wdt->wdd.info = &qcom_wdt_info;
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}
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wdt->wdd.ops = &qcom_wdt_ops;
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wdt->wdd.min_timeout = 1;
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wdt->wdd.max_timeout = 0x10000000U / wdt->rate;
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wdt->wdd.parent = dev;
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wdt->layout = data->offset;
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if (readl(wdt_addr(wdt, WDT_STS)) & 1)
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wdt->wdd.bootstatus = WDIOF_CARDRESET;
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/*
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* If 'timeout-sec' unspecified in devicetree, assume a 30 second
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* default, unless the max timeout is less than 30 seconds, then use
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* the max instead.
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*/
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wdt->wdd.timeout = min(wdt->wdd.max_timeout, 30U);
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watchdog_init_timeout(&wdt->wdd, 0, dev);
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/*
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* If WDT is already running, call WDT start which
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* will stop the WDT, set timeouts as bootloader
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* might use different ones and set running bit
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* to inform the WDT subsystem to ping the WDT
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*/
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if (qcom_wdt_is_running(&wdt->wdd)) {
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qcom_wdt_start(&wdt->wdd);
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set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
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}
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ret = devm_watchdog_register_device(dev, &wdt->wdd);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, wdt);
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return 0;
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}
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static int __maybe_unused qcom_wdt_suspend(struct device *dev)
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{
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struct qcom_wdt *wdt = dev_get_drvdata(dev);
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if (watchdog_active(&wdt->wdd))
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qcom_wdt_stop(&wdt->wdd);
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return 0;
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}
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static int __maybe_unused qcom_wdt_resume(struct device *dev)
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{
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struct qcom_wdt *wdt = dev_get_drvdata(dev);
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if (watchdog_active(&wdt->wdd))
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qcom_wdt_start(&wdt->wdd);
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return 0;
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}
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static const struct dev_pm_ops qcom_wdt_pm_ops = {
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SET_LATE_SYSTEM_SLEEP_PM_OPS(qcom_wdt_suspend, qcom_wdt_resume)
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};
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static const struct of_device_id qcom_wdt_of_table[] = {
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{ .compatible = "qcom,kpss-timer", .data = &match_data_apcs_tmr },
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{ .compatible = "qcom,scss-timer", .data = &match_data_apcs_tmr },
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{ .compatible = "qcom,kpss-wdt", .data = &match_data_kpss },
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{ },
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};
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MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
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static struct platform_driver qcom_watchdog_driver = {
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.probe = qcom_wdt_probe,
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = qcom_wdt_of_table,
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.pm = &qcom_wdt_pm_ops,
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},
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};
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module_platform_driver(qcom_watchdog_driver);
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MODULE_DESCRIPTION("QCOM KPSS Watchdog Driver");
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MODULE_LICENSE("GPL v2");
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