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![Christophe JAILLET](/assets/img/avatar_default.png)
The devm_clk_get_enabled() helper: - calls devm_clk_get() - calls clk_prepare_enable() and registers what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This simplifies the code and avoids the need of a dedicated function used with devm_add_action_or_reset(). Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/b1f8b5453791035ad534bd5ed36b49798ff4d9b2.1672418166.git.christophe.jaillet@wanadoo.fr Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
187 lines
4.7 KiB
C
187 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/N1 Watchdog timer.
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* This is a 12-bit timer driver from a (62.5/16384) MHz clock. It can't even
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* cope with 2 seconds.
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*
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* Copyright 2018 Renesas Electronics Europe Ltd.
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*
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* Derived from Ralink RT288x watchdog timer.
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/watchdog.h>
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#define DEFAULT_TIMEOUT 60
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#define RZN1_WDT_RETRIGGER 0x0
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#define RZN1_WDT_RETRIGGER_RELOAD_VAL 0
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#define RZN1_WDT_RETRIGGER_RELOAD_VAL_MASK 0xfff
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#define RZN1_WDT_RETRIGGER_PRESCALE BIT(12)
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#define RZN1_WDT_RETRIGGER_ENABLE BIT(13)
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#define RZN1_WDT_RETRIGGER_WDSI (0x2 << 14)
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#define RZN1_WDT_PRESCALER 16384
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#define RZN1_WDT_MAX 4095
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struct rzn1_watchdog {
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struct watchdog_device wdtdev;
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void __iomem *base;
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unsigned long clk_rate_khz;
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};
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static inline uint32_t max_heart_beat_ms(unsigned long clk_rate_khz)
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{
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return (RZN1_WDT_MAX * RZN1_WDT_PRESCALER) / clk_rate_khz;
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}
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static inline uint32_t compute_reload_value(uint32_t tick_ms,
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unsigned long clk_rate_khz)
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{
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return (tick_ms * clk_rate_khz) / RZN1_WDT_PRESCALER;
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}
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static int rzn1_wdt_ping(struct watchdog_device *w)
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{
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struct rzn1_watchdog *wdt = watchdog_get_drvdata(w);
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/* Any value retrigggers the watchdog */
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writel(0, wdt->base + RZN1_WDT_RETRIGGER);
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return 0;
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}
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static int rzn1_wdt_start(struct watchdog_device *w)
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{
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struct rzn1_watchdog *wdt = watchdog_get_drvdata(w);
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u32 val;
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/*
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* The hardware allows you to write to this reg only once.
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* Since this includes the reload value, there is no way to change the
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* timeout once started. Also note that the WDT clock is half the bus
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* fabric clock rate, so if the bus fabric clock rate is changed after
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* the WDT is started, the WDT interval will be wrong.
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*/
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val = RZN1_WDT_RETRIGGER_WDSI;
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val |= RZN1_WDT_RETRIGGER_ENABLE;
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val |= RZN1_WDT_RETRIGGER_PRESCALE;
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val |= compute_reload_value(w->max_hw_heartbeat_ms, wdt->clk_rate_khz);
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writel(val, wdt->base + RZN1_WDT_RETRIGGER);
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return 0;
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}
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static irqreturn_t rzn1_wdt_irq(int irq, void *_wdt)
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{
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pr_crit("RZN1 Watchdog. Initiating system reboot\n");
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emergency_restart();
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return IRQ_HANDLED;
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}
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static struct watchdog_info rzn1_wdt_info = {
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.identity = "RZ/N1 Watchdog",
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.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
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};
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static const struct watchdog_ops rzn1_wdt_ops = {
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.owner = THIS_MODULE,
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.start = rzn1_wdt_start,
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.ping = rzn1_wdt_ping,
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};
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static int rzn1_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rzn1_watchdog *wdt;
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struct device_node *np = dev->of_node;
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struct clk *clk;
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unsigned long clk_rate;
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int ret;
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int irq;
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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wdt->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(wdt->base))
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return PTR_ERR(wdt->base);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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ret = devm_request_irq(dev, irq, rzn1_wdt_irq, 0,
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np->name, wdt);
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if (ret) {
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dev_err(dev, "failed to request irq %d\n", irq);
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return ret;
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}
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clk = devm_clk_get_enabled(dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to get the clock\n");
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return PTR_ERR(clk);
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}
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clk_rate = clk_get_rate(clk);
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if (!clk_rate) {
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dev_err(dev, "failed to get the clock rate\n");
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return -EINVAL;
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}
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wdt->clk_rate_khz = clk_rate / 1000;
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wdt->wdtdev.info = &rzn1_wdt_info,
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wdt->wdtdev.ops = &rzn1_wdt_ops,
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wdt->wdtdev.status = WATCHDOG_NOWAYOUT_INIT_STATUS,
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wdt->wdtdev.parent = dev;
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/*
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* The period of the watchdog cannot be changed once set
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* and is limited to a very short period.
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* Configure it for a 1s period once and for all, and
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* rely on the heart-beat provided by the watchdog core
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* to make this usable by the user-space.
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*/
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wdt->wdtdev.max_hw_heartbeat_ms = max_heart_beat_ms(wdt->clk_rate_khz);
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if (wdt->wdtdev.max_hw_heartbeat_ms > 1000)
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wdt->wdtdev.max_hw_heartbeat_ms = 1000;
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wdt->wdtdev.timeout = DEFAULT_TIMEOUT;
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ret = watchdog_init_timeout(&wdt->wdtdev, 0, dev);
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if (ret)
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return ret;
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watchdog_set_drvdata(&wdt->wdtdev, wdt);
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return devm_watchdog_register_device(dev, &wdt->wdtdev);
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}
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static const struct of_device_id rzn1_wdt_match[] = {
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{ .compatible = "renesas,rzn1-wdt" },
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{},
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};
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MODULE_DEVICE_TABLE(of, rzn1_wdt_match);
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static struct platform_driver rzn1_wdt_driver = {
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.probe = rzn1_wdt_probe,
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = rzn1_wdt_match,
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},
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};
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module_platform_driver(rzn1_wdt_driver);
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MODULE_DESCRIPTION("Renesas RZ/N1 hardware watchdog");
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MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
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MODULE_LICENSE("GPL");
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