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Most of the display controller's registers are double-buffered, a few of them are triple-buffered. The ASSEMBLY shadow copy is latched intto the ACTIVE copy for double-buffered registers. For triple-buffered registers the ASSEMBLY copy is first latched into the ARM copy. Latching into the ACTIVE copy happens immediately if the controller is inactive. Otherwise the latching happens on the next frame boundary. The latching of the ASSEMBLY into the ARM copy happens immediately. Latching is controlled by a set of *_ACT_REQ and *_UPDATE bits in the DC_CMD_STATE_CONTROL register. Signed-off-by: Thierry Reding <treding@nvidia.com> |
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| .. | ||
| dc.c | ||
| dc.h | ||
| dpaux.c | ||
| dpaux.h | ||
| drm.c | ||
| drm.h | ||
| dsi.c | ||
| dsi.h | ||
| fb.c | ||
| gem.c | ||
| gem.h | ||
| gr2d.c | ||
| gr2d.h | ||
| gr3d.c | ||
| gr3d.h | ||
| hdmi.c | ||
| hdmi.h | ||
| Kconfig | ||
| Makefile | ||
| mipi-phy.c | ||
| mipi-phy.h | ||
| output.c | ||
| rgb.c | ||
| sor.c | ||
| sor.h | ||