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![Miaohe Lin](/assets/img/avatar_default.png)
Commit13db77347d
("KVM: x86: don't notify userspace IOAPIC on edge EOI") said, edge-triggered interrupts don't set a bit in TMR, which means that IOAPIC isn't notified on EOI. And var level indicates level-triggered interrupt. But commit3159d36ad7
("KVM: x86: use generic function for MSI parsing") replace var level with irq.level by mistake. Fix it by changing irq.level to irq.trig_mode. Cc: stable@vger.kernel.org Fixes:3159d36ad7
("KVM: x86: use generic function for MSI parsing") Signed-off-by: Miaohe Lin <linmiaohe@huawei.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
432 lines
11 KiB
C
432 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* irq_comm.c: Common API for in kernel interrupt controller
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* Copyright (c) 2007, Intel Corporation.
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*
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* Authors:
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* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
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*
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* Copyright 2010 Red Hat, Inc. and/or its affiliates.
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*/
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#include <linux/kvm_host.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/rculist.h>
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#include <trace/events/kvm.h>
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#include <asm/msidef.h>
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#include "irq.h"
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#include "ioapic.h"
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#include "lapic.h"
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#include "hyperv.h"
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#include "x86.h"
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static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
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struct kvm *kvm, int irq_source_id, int level,
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bool line_status)
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{
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struct kvm_pic *pic = kvm->arch.vpic;
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return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level);
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}
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static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
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struct kvm *kvm, int irq_source_id, int level,
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bool line_status)
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{
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struct kvm_ioapic *ioapic = kvm->arch.vioapic;
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return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level,
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line_status);
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}
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int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
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struct kvm_lapic_irq *irq, struct dest_map *dest_map)
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{
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int i, r = -1;
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struct kvm_vcpu *vcpu, *lowest = NULL;
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unsigned long dest_vcpu_bitmap[BITS_TO_LONGS(KVM_MAX_VCPUS)];
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unsigned int dest_vcpus = 0;
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if (kvm_irq_delivery_to_apic_fast(kvm, src, irq, &r, dest_map))
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return r;
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if (irq->dest_mode == APIC_DEST_PHYSICAL &&
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irq->dest_id == 0xff && kvm_lowest_prio_delivery(irq)) {
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printk(KERN_INFO "kvm: apic: phys broadcast and lowest prio\n");
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irq->delivery_mode = APIC_DM_FIXED;
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}
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memset(dest_vcpu_bitmap, 0, sizeof(dest_vcpu_bitmap));
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kvm_for_each_vcpu(i, vcpu, kvm) {
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if (!kvm_apic_present(vcpu))
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continue;
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if (!kvm_apic_match_dest(vcpu, src, irq->shorthand,
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irq->dest_id, irq->dest_mode))
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continue;
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if (!kvm_lowest_prio_delivery(irq)) {
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if (r < 0)
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r = 0;
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r += kvm_apic_set_irq(vcpu, irq, dest_map);
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} else if (kvm_apic_sw_enabled(vcpu->arch.apic)) {
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if (!kvm_vector_hashing_enabled()) {
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if (!lowest)
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lowest = vcpu;
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else if (kvm_apic_compare_prio(vcpu, lowest) < 0)
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lowest = vcpu;
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} else {
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__set_bit(i, dest_vcpu_bitmap);
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dest_vcpus++;
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}
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}
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}
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if (dest_vcpus != 0) {
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int idx = kvm_vector_to_index(irq->vector, dest_vcpus,
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dest_vcpu_bitmap, KVM_MAX_VCPUS);
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lowest = kvm_get_vcpu(kvm, idx);
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}
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if (lowest)
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r = kvm_apic_set_irq(lowest, irq, dest_map);
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return r;
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}
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void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
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struct kvm_lapic_irq *irq)
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{
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trace_kvm_msi_set_irq(e->msi.address_lo | (kvm->arch.x2apic_format ?
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(u64)e->msi.address_hi << 32 : 0),
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e->msi.data);
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irq->dest_id = (e->msi.address_lo &
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MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
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if (kvm->arch.x2apic_format)
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irq->dest_id |= MSI_ADDR_EXT_DEST_ID(e->msi.address_hi);
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irq->vector = (e->msi.data &
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MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
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irq->dest_mode = kvm_lapic_irq_dest_mode(
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!!((1 << MSI_ADDR_DEST_MODE_SHIFT) & e->msi.address_lo));
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irq->trig_mode = (1 << MSI_DATA_TRIGGER_SHIFT) & e->msi.data;
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irq->delivery_mode = e->msi.data & 0x700;
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irq->msi_redir_hint = ((e->msi.address_lo
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& MSI_ADDR_REDIRECTION_LOWPRI) > 0);
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irq->level = 1;
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irq->shorthand = APIC_DEST_NOSHORT;
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}
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EXPORT_SYMBOL_GPL(kvm_set_msi_irq);
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static inline bool kvm_msi_route_invalid(struct kvm *kvm,
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struct kvm_kernel_irq_routing_entry *e)
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{
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return kvm->arch.x2apic_format && (e->msi.address_hi & 0xff);
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}
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int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
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struct kvm *kvm, int irq_source_id, int level, bool line_status)
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{
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struct kvm_lapic_irq irq;
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if (kvm_msi_route_invalid(kvm, e))
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return -EINVAL;
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if (!level)
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return -1;
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kvm_set_msi_irq(kvm, e, &irq);
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return kvm_irq_delivery_to_apic(kvm, NULL, &irq, NULL);
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}
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static int kvm_hv_set_sint(struct kvm_kernel_irq_routing_entry *e,
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struct kvm *kvm, int irq_source_id, int level,
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bool line_status)
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{
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if (!level)
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return -1;
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return kvm_hv_synic_set_irq(kvm, e->hv_sint.vcpu, e->hv_sint.sint);
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}
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int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e,
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struct kvm *kvm, int irq_source_id, int level,
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bool line_status)
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{
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struct kvm_lapic_irq irq;
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int r;
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switch (e->type) {
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case KVM_IRQ_ROUTING_HV_SINT:
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return kvm_hv_set_sint(e, kvm, irq_source_id, level,
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line_status);
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case KVM_IRQ_ROUTING_MSI:
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if (kvm_msi_route_invalid(kvm, e))
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return -EINVAL;
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kvm_set_msi_irq(kvm, e, &irq);
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if (kvm_irq_delivery_to_apic_fast(kvm, NULL, &irq, &r, NULL))
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return r;
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break;
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default:
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break;
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}
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return -EWOULDBLOCK;
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}
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int kvm_request_irq_source_id(struct kvm *kvm)
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{
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unsigned long *bitmap = &kvm->arch.irq_sources_bitmap;
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int irq_source_id;
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mutex_lock(&kvm->irq_lock);
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irq_source_id = find_first_zero_bit(bitmap, BITS_PER_LONG);
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if (irq_source_id >= BITS_PER_LONG) {
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printk(KERN_WARNING "kvm: exhaust allocatable IRQ sources!\n");
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irq_source_id = -EFAULT;
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goto unlock;
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}
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ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
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ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
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set_bit(irq_source_id, bitmap);
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unlock:
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mutex_unlock(&kvm->irq_lock);
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return irq_source_id;
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}
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void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
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{
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ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
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ASSERT(irq_source_id != KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID);
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mutex_lock(&kvm->irq_lock);
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if (irq_source_id < 0 ||
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irq_source_id >= BITS_PER_LONG) {
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printk(KERN_ERR "kvm: IRQ source ID out of range!\n");
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goto unlock;
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}
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clear_bit(irq_source_id, &kvm->arch.irq_sources_bitmap);
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if (!irqchip_kernel(kvm))
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goto unlock;
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kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id);
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kvm_pic_clear_all(kvm->arch.vpic, irq_source_id);
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unlock:
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mutex_unlock(&kvm->irq_lock);
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}
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void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
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struct kvm_irq_mask_notifier *kimn)
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{
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mutex_lock(&kvm->irq_lock);
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kimn->irq = irq;
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hlist_add_head_rcu(&kimn->link, &kvm->arch.mask_notifier_list);
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mutex_unlock(&kvm->irq_lock);
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}
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void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
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struct kvm_irq_mask_notifier *kimn)
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{
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mutex_lock(&kvm->irq_lock);
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hlist_del_rcu(&kimn->link);
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mutex_unlock(&kvm->irq_lock);
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synchronize_srcu(&kvm->irq_srcu);
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}
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void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
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bool mask)
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{
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struct kvm_irq_mask_notifier *kimn;
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int idx, gsi;
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idx = srcu_read_lock(&kvm->irq_srcu);
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gsi = kvm_irq_map_chip_pin(kvm, irqchip, pin);
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if (gsi != -1)
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hlist_for_each_entry_rcu(kimn, &kvm->arch.mask_notifier_list, link)
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if (kimn->irq == gsi)
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kimn->func(kimn, mask);
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srcu_read_unlock(&kvm->irq_srcu, idx);
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}
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bool kvm_arch_can_set_irq_routing(struct kvm *kvm)
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{
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return irqchip_in_kernel(kvm);
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}
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int kvm_set_routing_entry(struct kvm *kvm,
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struct kvm_kernel_irq_routing_entry *e,
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const struct kvm_irq_routing_entry *ue)
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{
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/* We can't check irqchip_in_kernel() here as some callers are
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* currently inititalizing the irqchip. Other callers should therefore
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* check kvm_arch_can_set_irq_routing() before calling this function.
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*/
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switch (ue->type) {
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case KVM_IRQ_ROUTING_IRQCHIP:
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if (irqchip_split(kvm))
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return -EINVAL;
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e->irqchip.pin = ue->u.irqchip.pin;
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switch (ue->u.irqchip.irqchip) {
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case KVM_IRQCHIP_PIC_SLAVE:
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e->irqchip.pin += PIC_NUM_PINS / 2;
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/* fall through */
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case KVM_IRQCHIP_PIC_MASTER:
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if (ue->u.irqchip.pin >= PIC_NUM_PINS / 2)
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return -EINVAL;
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e->set = kvm_set_pic_irq;
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break;
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case KVM_IRQCHIP_IOAPIC:
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if (ue->u.irqchip.pin >= KVM_IOAPIC_NUM_PINS)
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return -EINVAL;
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e->set = kvm_set_ioapic_irq;
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break;
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default:
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return -EINVAL;
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}
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e->irqchip.irqchip = ue->u.irqchip.irqchip;
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break;
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case KVM_IRQ_ROUTING_MSI:
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e->set = kvm_set_msi;
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e->msi.address_lo = ue->u.msi.address_lo;
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e->msi.address_hi = ue->u.msi.address_hi;
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e->msi.data = ue->u.msi.data;
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if (kvm_msi_route_invalid(kvm, e))
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return -EINVAL;
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break;
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case KVM_IRQ_ROUTING_HV_SINT:
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e->set = kvm_hv_set_sint;
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e->hv_sint.vcpu = ue->u.hv_sint.vcpu;
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e->hv_sint.sint = ue->u.hv_sint.sint;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
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struct kvm_vcpu **dest_vcpu)
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{
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int i, r = 0;
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struct kvm_vcpu *vcpu;
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if (kvm_intr_is_single_vcpu_fast(kvm, irq, dest_vcpu))
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return true;
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kvm_for_each_vcpu(i, vcpu, kvm) {
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if (!kvm_apic_present(vcpu))
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continue;
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if (!kvm_apic_match_dest(vcpu, NULL, irq->shorthand,
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irq->dest_id, irq->dest_mode))
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continue;
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if (++r == 2)
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return false;
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*dest_vcpu = vcpu;
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}
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return r == 1;
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}
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EXPORT_SYMBOL_GPL(kvm_intr_is_single_vcpu);
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#define IOAPIC_ROUTING_ENTRY(irq) \
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{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
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.u.irqchip = { .irqchip = KVM_IRQCHIP_IOAPIC, .pin = (irq) } }
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#define ROUTING_ENTRY1(irq) IOAPIC_ROUTING_ENTRY(irq)
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#define PIC_ROUTING_ENTRY(irq) \
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{ .gsi = irq, .type = KVM_IRQ_ROUTING_IRQCHIP, \
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.u.irqchip = { .irqchip = SELECT_PIC(irq), .pin = (irq) % 8 } }
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#define ROUTING_ENTRY2(irq) \
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IOAPIC_ROUTING_ENTRY(irq), PIC_ROUTING_ENTRY(irq)
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static const struct kvm_irq_routing_entry default_routing[] = {
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ROUTING_ENTRY2(0), ROUTING_ENTRY2(1),
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ROUTING_ENTRY2(2), ROUTING_ENTRY2(3),
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ROUTING_ENTRY2(4), ROUTING_ENTRY2(5),
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ROUTING_ENTRY2(6), ROUTING_ENTRY2(7),
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ROUTING_ENTRY2(8), ROUTING_ENTRY2(9),
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ROUTING_ENTRY2(10), ROUTING_ENTRY2(11),
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ROUTING_ENTRY2(12), ROUTING_ENTRY2(13),
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ROUTING_ENTRY2(14), ROUTING_ENTRY2(15),
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ROUTING_ENTRY1(16), ROUTING_ENTRY1(17),
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ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
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ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
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ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
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};
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int kvm_setup_default_irq_routing(struct kvm *kvm)
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{
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return kvm_set_irq_routing(kvm, default_routing,
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ARRAY_SIZE(default_routing), 0);
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}
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static const struct kvm_irq_routing_entry empty_routing[] = {};
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int kvm_setup_empty_irq_routing(struct kvm *kvm)
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{
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return kvm_set_irq_routing(kvm, empty_routing, 0, 0);
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}
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void kvm_arch_post_irq_routing_update(struct kvm *kvm)
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{
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if (!irqchip_split(kvm))
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return;
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kvm_make_scan_ioapic_request(kvm);
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}
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void kvm_scan_ioapic_routes(struct kvm_vcpu *vcpu,
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ulong *ioapic_handled_vectors)
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{
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struct kvm *kvm = vcpu->kvm;
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struct kvm_kernel_irq_routing_entry *entry;
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struct kvm_irq_routing_table *table;
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u32 i, nr_ioapic_pins;
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int idx;
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idx = srcu_read_lock(&kvm->irq_srcu);
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table = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
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nr_ioapic_pins = min_t(u32, table->nr_rt_entries,
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kvm->arch.nr_reserved_ioapic_pins);
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for (i = 0; i < nr_ioapic_pins; ++i) {
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hlist_for_each_entry(entry, &table->map[i], link) {
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struct kvm_lapic_irq irq;
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if (entry->type != KVM_IRQ_ROUTING_MSI)
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continue;
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kvm_set_msi_irq(vcpu->kvm, entry, &irq);
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if (irq.trig_mode &&
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kvm_apic_match_dest(vcpu, NULL, APIC_DEST_NOSHORT,
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irq.dest_id, irq.dest_mode))
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__set_bit(irq.vector, ioapic_handled_vectors);
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}
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}
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srcu_read_unlock(&kvm->irq_srcu, idx);
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}
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void kvm_arch_irq_routing_update(struct kvm *kvm)
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{
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kvm_hv_irq_routing_update(kvm);
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}
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