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![Jarkko Sakkinen](/assets/img/avatar_default.png)
Wrong call order.
Reported-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Fixes: 74d6b3ceaa
Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
cc: stable@vger.kernel.org
377 lines
8.3 KiB
C
377 lines
8.3 KiB
C
/*
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* Copyright (C) 2014 Intel Corporation
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*
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* Authors:
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* Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
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*
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* Maintained by: <tpmdd-devel@lists.sourceforge.net>
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*
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* This device driver implements the TPM interface as defined in
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* the TCG CRB 2.0 TPM specification.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/acpi.h>
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#include <linux/highmem.h>
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#include <linux/rculist.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "tpm.h"
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#define ACPI_SIG_TPM2 "TPM2"
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static const u8 CRB_ACPI_START_UUID[] = {
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/* 0000 */ 0xAB, 0x6C, 0xBF, 0x6B, 0x63, 0x54, 0x14, 0x47,
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/* 0008 */ 0xB7, 0xCD, 0xF0, 0x20, 0x3C, 0x03, 0x68, 0xD4
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};
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enum crb_defaults {
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CRB_ACPI_START_REVISION_ID = 1,
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CRB_ACPI_START_INDEX = 1,
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};
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enum crb_ca_request {
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CRB_CA_REQ_GO_IDLE = BIT(0),
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CRB_CA_REQ_CMD_READY = BIT(1),
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};
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enum crb_ca_status {
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CRB_CA_STS_ERROR = BIT(0),
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CRB_CA_STS_TPM_IDLE = BIT(1),
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};
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enum crb_start {
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CRB_START_INVOKE = BIT(0),
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};
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enum crb_cancel {
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CRB_CANCEL_INVOKE = BIT(0),
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};
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struct crb_control_area {
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u32 req;
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u32 sts;
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u32 cancel;
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u32 start;
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u32 int_enable;
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u32 int_sts;
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u32 cmd_size;
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u32 cmd_pa_low;
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u32 cmd_pa_high;
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u32 rsp_size;
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u64 rsp_pa;
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} __packed;
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enum crb_status {
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CRB_STS_COMPLETE = BIT(0),
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};
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enum crb_flags {
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CRB_FL_ACPI_START = BIT(0),
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CRB_FL_CRB_START = BIT(1),
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};
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struct crb_priv {
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unsigned int flags;
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struct resource res;
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void __iomem *iobase;
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struct crb_control_area __iomem *cca;
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u8 __iomem *cmd;
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u8 __iomem *rsp;
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};
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static SIMPLE_DEV_PM_OPS(crb_pm, tpm_pm_suspend, tpm_pm_resume);
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static u8 crb_status(struct tpm_chip *chip)
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{
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struct crb_priv *priv = chip->vendor.priv;
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u8 sts = 0;
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if ((ioread32(&priv->cca->start) & CRB_START_INVOKE) !=
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CRB_START_INVOKE)
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sts |= CRB_STS_COMPLETE;
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return sts;
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}
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static int crb_recv(struct tpm_chip *chip, u8 *buf, size_t count)
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{
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struct crb_priv *priv = chip->vendor.priv;
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unsigned int expected;
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/* sanity check */
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if (count < 6)
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return -EIO;
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if (ioread32(&priv->cca->sts) & CRB_CA_STS_ERROR)
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return -EIO;
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memcpy_fromio(buf, priv->rsp, 6);
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expected = be32_to_cpup((__be32 *) &buf[2]);
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if (expected > count)
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return -EIO;
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memcpy_fromio(&buf[6], &priv->rsp[6], expected - 6);
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return expected;
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}
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static int crb_do_acpi_start(struct tpm_chip *chip)
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{
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union acpi_object *obj;
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int rc;
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obj = acpi_evaluate_dsm(chip->acpi_dev_handle,
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CRB_ACPI_START_UUID,
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CRB_ACPI_START_REVISION_ID,
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CRB_ACPI_START_INDEX,
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NULL);
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if (!obj)
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return -ENXIO;
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rc = obj->integer.value == 0 ? 0 : -ENXIO;
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ACPI_FREE(obj);
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return rc;
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}
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static int crb_send(struct tpm_chip *chip, u8 *buf, size_t len)
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{
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struct crb_priv *priv = chip->vendor.priv;
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int rc = 0;
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if (len > ioread32(&priv->cca->cmd_size)) {
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dev_err(&chip->dev,
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"invalid command count value %x %zx\n",
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(unsigned int) len,
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(size_t) ioread32(&priv->cca->cmd_size));
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return -E2BIG;
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}
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memcpy_toio(priv->cmd, buf, len);
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/* Make sure that cmd is populated before issuing start. */
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wmb();
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if (priv->flags & CRB_FL_CRB_START)
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iowrite32(cpu_to_le32(CRB_START_INVOKE), &priv->cca->start);
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if (priv->flags & CRB_FL_ACPI_START)
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rc = crb_do_acpi_start(chip);
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return rc;
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}
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static void crb_cancel(struct tpm_chip *chip)
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{
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struct crb_priv *priv = chip->vendor.priv;
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iowrite32(cpu_to_le32(CRB_CANCEL_INVOKE), &priv->cca->cancel);
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/* Make sure that cmd is populated before issuing cancel. */
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wmb();
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if ((priv->flags & CRB_FL_ACPI_START) && crb_do_acpi_start(chip))
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dev_err(&chip->dev, "ACPI Start failed\n");
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iowrite32(0, &priv->cca->cancel);
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}
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static bool crb_req_canceled(struct tpm_chip *chip, u8 status)
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{
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struct crb_priv *priv = chip->vendor.priv;
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u32 cancel = ioread32(&priv->cca->cancel);
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return (cancel & CRB_CANCEL_INVOKE) == CRB_CANCEL_INVOKE;
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}
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static const struct tpm_class_ops tpm_crb = {
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.status = crb_status,
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.recv = crb_recv,
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.send = crb_send,
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.cancel = crb_cancel,
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.req_canceled = crb_req_canceled,
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.req_complete_mask = CRB_STS_COMPLETE,
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.req_complete_val = CRB_STS_COMPLETE,
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};
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static int crb_init(struct acpi_device *device, struct crb_priv *priv)
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{
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struct tpm_chip *chip;
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int rc;
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chip = tpmm_chip_alloc(&device->dev, &tpm_crb);
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if (IS_ERR(chip))
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return PTR_ERR(chip);
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chip->vendor.priv = priv;
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chip->acpi_dev_handle = device->handle;
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chip->flags = TPM_CHIP_FLAG_TPM2;
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rc = tpm_get_timeouts(chip);
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if (rc)
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return rc;
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rc = tpm2_do_selftest(chip);
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if (rc)
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return rc;
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return tpm_chip_register(chip);
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}
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static int crb_check_resource(struct acpi_resource *ares, void *data)
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{
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struct crb_priv *priv = data;
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struct resource res;
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if (acpi_dev_resource_memory(ares, &res)) {
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priv->res = res;
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priv->res.name = NULL;
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}
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return 1;
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}
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static void __iomem *crb_map_res(struct device *dev, struct crb_priv *priv,
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u64 start, u32 size)
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{
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struct resource new_res = {
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.start = start,
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.end = start + size - 1,
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.flags = IORESOURCE_MEM,
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};
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/* Detect a 64 bit address on a 32 bit system */
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if (start != new_res.start)
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return ERR_PTR(-EINVAL);
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if (!resource_contains(&priv->res, &new_res))
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return devm_ioremap_resource(dev, &new_res);
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return priv->iobase + (new_res.start - priv->res.start);
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}
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static int crb_map_io(struct acpi_device *device, struct crb_priv *priv,
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struct acpi_table_tpm2 *buf)
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{
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struct list_head resources;
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struct device *dev = &device->dev;
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u64 pa;
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int ret;
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INIT_LIST_HEAD(&resources);
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ret = acpi_dev_get_resources(device, &resources, crb_check_resource,
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priv);
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if (ret < 0)
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return ret;
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acpi_dev_free_resource_list(&resources);
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if (resource_type(&priv->res) != IORESOURCE_MEM) {
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dev_err(dev,
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FW_BUG "TPM2 ACPI table does not define a memory resource\n");
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return -EINVAL;
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}
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priv->iobase = devm_ioremap_resource(dev, &priv->res);
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if (IS_ERR(priv->iobase))
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return PTR_ERR(priv->iobase);
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priv->cca = crb_map_res(dev, priv, buf->control_address, 0x1000);
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if (IS_ERR(priv->cca))
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return PTR_ERR(priv->cca);
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pa = ((u64) ioread32(&priv->cca->cmd_pa_high) << 32) |
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(u64) ioread32(&priv->cca->cmd_pa_low);
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priv->cmd = crb_map_res(dev, priv, pa, ioread32(&priv->cca->cmd_size));
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if (IS_ERR(priv->cmd))
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return PTR_ERR(priv->cmd);
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memcpy_fromio(&pa, &priv->cca->rsp_pa, 8);
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pa = le64_to_cpu(pa);
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priv->rsp = crb_map_res(dev, priv, pa, ioread32(&priv->cca->rsp_size));
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return PTR_ERR_OR_ZERO(priv->rsp);
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}
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static int crb_acpi_add(struct acpi_device *device)
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{
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struct acpi_table_tpm2 *buf;
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struct crb_priv *priv;
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struct device *dev = &device->dev;
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acpi_status status;
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u32 sm;
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int rc;
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status = acpi_get_table(ACPI_SIG_TPM2, 1,
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(struct acpi_table_header **) &buf);
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if (ACPI_FAILURE(status) || buf->header.length < sizeof(*buf)) {
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dev_err(dev, FW_BUG "failed to get TPM2 ACPI table\n");
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return -EINVAL;
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}
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/* Should the FIFO driver handle this? */
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sm = buf->start_method;
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if (sm == ACPI_TPM2_MEMORY_MAPPED)
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return -ENODEV;
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priv = devm_kzalloc(dev, sizeof(struct crb_priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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/* The reason for the extra quirk is that the PTT in 4th Gen Core CPUs
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* report only ACPI start but in practice seems to require both
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* ACPI start and CRB start.
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*/
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if (sm == ACPI_TPM2_COMMAND_BUFFER || sm == ACPI_TPM2_MEMORY_MAPPED ||
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!strcmp(acpi_device_hid(device), "MSFT0101"))
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priv->flags |= CRB_FL_CRB_START;
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if (sm == ACPI_TPM2_START_METHOD ||
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sm == ACPI_TPM2_COMMAND_BUFFER_WITH_START_METHOD)
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priv->flags |= CRB_FL_ACPI_START;
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rc = crb_map_io(device, priv, buf);
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if (rc)
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return rc;
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return crb_init(device, priv);
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}
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static int crb_acpi_remove(struct acpi_device *device)
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{
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struct device *dev = &device->dev;
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struct tpm_chip *chip = dev_get_drvdata(dev);
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if (chip->flags & TPM_CHIP_FLAG_TPM2)
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tpm2_shutdown(chip, TPM2_SU_CLEAR);
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tpm_chip_unregister(chip);
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return 0;
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}
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static struct acpi_device_id crb_device_ids[] = {
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{"MSFT0101", 0},
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{"", 0},
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};
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MODULE_DEVICE_TABLE(acpi, crb_device_ids);
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static struct acpi_driver crb_acpi_driver = {
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.name = "tpm_crb",
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.ids = crb_device_ids,
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.ops = {
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.add = crb_acpi_add,
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.remove = crb_acpi_remove,
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},
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.drv = {
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.pm = &crb_pm,
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},
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};
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module_acpi_driver(crb_acpi_driver);
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MODULE_AUTHOR("Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>");
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MODULE_DESCRIPTION("TPM2 Driver");
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MODULE_VERSION("0.1");
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MODULE_LICENSE("GPL");
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