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![Jaehoon Chung](/assets/img/avatar_default.png)
This patch removes the prepare_command hook from entire dw_mmc driver. Now, almost all SoCs are using by default, except Exynos. It seems that dwmmc controller is using unnecessary hook. To know whether needs to set this bit or not, add the DW_MMC_CARD_NO_USE_HOLD bit. If some SoCs need to disable this in future, just set the DW_MMC_CARD_NO_USE_HOLD bit. set_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags), Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
307 lines
7.5 KiB
C
307 lines
7.5 KiB
C
/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/dw_mmc.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#define RK3288_CLKGEN_DIV 2
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struct dw_mci_rockchip_priv_data {
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struct clk *drv_clk;
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struct clk *sample_clk;
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int default_sample_phase;
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};
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static int dw_mci_rk3288_setup_clock(struct dw_mci *host)
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{
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host->bus_hz /= RK3288_CLKGEN_DIV;
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return 0;
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}
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static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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struct dw_mci_rockchip_priv_data *priv = host->priv;
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int ret;
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unsigned int cclkin;
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u32 bus_hz;
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if (ios->clock == 0)
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return;
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/*
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* cclkin: source clock of mmc controller
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* bus_hz: card interface clock generated by CLKGEN
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* bus_hz = cclkin / RK3288_CLKGEN_DIV
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* ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
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*
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* Note: div can only be 0 or 1
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* if DDR50 8bit mode(only emmc work in 8bit mode),
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* div must be set 1
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*/
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if (ios->bus_width == MMC_BUS_WIDTH_8 &&
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ios->timing == MMC_TIMING_MMC_DDR52)
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cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
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else
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cclkin = ios->clock * RK3288_CLKGEN_DIV;
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ret = clk_set_rate(host->ciu_clk, cclkin);
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if (ret)
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dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
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bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
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if (bus_hz != host->bus_hz) {
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host->bus_hz = bus_hz;
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/* force dw_mci_setup_bus() */
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host->current_speed = 0;
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}
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/* Make sure we use phases which we can enumerate with */
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if (!IS_ERR(priv->sample_clk))
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clk_set_phase(priv->sample_clk, priv->default_sample_phase);
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}
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#define NUM_PHASES 360
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#define TUNING_ITERATION_TO_PHASE(i) (DIV_ROUND_UP((i) * 360, NUM_PHASES))
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static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
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{
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struct dw_mci *host = slot->host;
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struct dw_mci_rockchip_priv_data *priv = host->priv;
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struct mmc_host *mmc = slot->mmc;
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int ret = 0;
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int i;
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bool v, prev_v = 0, first_v;
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struct range_t {
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int start;
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int end; /* inclusive */
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};
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struct range_t *ranges;
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unsigned int range_count = 0;
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int longest_range_len = -1;
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int longest_range = -1;
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int middle_phase;
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if (IS_ERR(priv->sample_clk)) {
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dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
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return -EIO;
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}
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ranges = kmalloc_array(NUM_PHASES / 2 + 1, sizeof(*ranges), GFP_KERNEL);
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if (!ranges)
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return -ENOMEM;
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/* Try each phase and extract good ranges */
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for (i = 0; i < NUM_PHASES; ) {
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clk_set_phase(priv->sample_clk, TUNING_ITERATION_TO_PHASE(i));
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v = !mmc_send_tuning(mmc, opcode, NULL);
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if (i == 0)
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first_v = v;
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if ((!prev_v) && v) {
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range_count++;
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ranges[range_count-1].start = i;
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}
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if (v) {
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ranges[range_count-1].end = i;
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i++;
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} else if (i == NUM_PHASES - 1) {
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/* No extra skipping rules if we're at the end */
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i++;
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} else {
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/*
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* No need to check too close to an invalid
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* one since testing bad phases is slow. Skip
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* 20 degrees.
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*/
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i += DIV_ROUND_UP(20 * NUM_PHASES, 360);
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/* Always test the last one */
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if (i >= NUM_PHASES)
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i = NUM_PHASES - 1;
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}
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prev_v = v;
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}
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if (range_count == 0) {
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dev_warn(host->dev, "All phases bad!");
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ret = -EIO;
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goto free;
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}
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/* wrap around case, merge the end points */
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if ((range_count > 1) && first_v && v) {
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ranges[0].start = ranges[range_count-1].start;
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range_count--;
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}
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if (ranges[0].start == 0 && ranges[0].end == NUM_PHASES - 1) {
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clk_set_phase(priv->sample_clk, priv->default_sample_phase);
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dev_info(host->dev, "All phases work, using default phase %d.",
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priv->default_sample_phase);
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goto free;
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}
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/* Find the longest range */
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for (i = 0; i < range_count; i++) {
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int len = (ranges[i].end - ranges[i].start + 1);
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if (len < 0)
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len += NUM_PHASES;
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if (longest_range_len < len) {
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longest_range_len = len;
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longest_range = i;
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}
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dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
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TUNING_ITERATION_TO_PHASE(ranges[i].start),
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TUNING_ITERATION_TO_PHASE(ranges[i].end),
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len
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);
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}
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dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
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TUNING_ITERATION_TO_PHASE(ranges[longest_range].start),
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TUNING_ITERATION_TO_PHASE(ranges[longest_range].end),
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longest_range_len
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);
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middle_phase = ranges[longest_range].start + longest_range_len / 2;
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middle_phase %= NUM_PHASES;
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dev_info(host->dev, "Successfully tuned phase to %d\n",
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TUNING_ITERATION_TO_PHASE(middle_phase));
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clk_set_phase(priv->sample_clk,
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TUNING_ITERATION_TO_PHASE(middle_phase));
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free:
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kfree(ranges);
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return ret;
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}
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static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
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{
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struct device_node *np = host->dev->of_node;
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struct dw_mci_rockchip_priv_data *priv;
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priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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if (of_property_read_u32(np, "rockchip,default-sample-phase",
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&priv->default_sample_phase))
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priv->default_sample_phase = 0;
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priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
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if (IS_ERR(priv->drv_clk))
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dev_dbg(host->dev, "ciu_drv not available\n");
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priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
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if (IS_ERR(priv->sample_clk))
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dev_dbg(host->dev, "ciu_sample not available\n");
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host->priv = priv;
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return 0;
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}
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static int dw_mci_rockchip_init(struct dw_mci *host)
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{
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/* It is slot 8 on Rockchip SoCs */
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host->sdio_id0 = 8;
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/* It needs this quirk on all Rockchip SoCs */
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host->pdata->quirks |= DW_MCI_QUIRK_BROKEN_DTO;
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return 0;
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}
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static const struct dw_mci_drv_data rk2928_drv_data = {
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.init = dw_mci_rockchip_init,
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};
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static const struct dw_mci_drv_data rk3288_drv_data = {
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.set_ios = dw_mci_rk3288_set_ios,
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.execute_tuning = dw_mci_rk3288_execute_tuning,
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.parse_dt = dw_mci_rk3288_parse_dt,
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.setup_clock = dw_mci_rk3288_setup_clock,
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.init = dw_mci_rockchip_init,
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};
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static const struct of_device_id dw_mci_rockchip_match[] = {
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{ .compatible = "rockchip,rk2928-dw-mshc",
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.data = &rk2928_drv_data },
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{ .compatible = "rockchip,rk3288-dw-mshc",
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.data = &rk3288_drv_data },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
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static int dw_mci_rockchip_probe(struct platform_device *pdev)
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{
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const struct dw_mci_drv_data *drv_data;
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const struct of_device_id *match;
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if (!pdev->dev.of_node)
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return -ENODEV;
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match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
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drv_data = match->data;
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return dw_mci_pltfm_register(pdev, drv_data);
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}
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#ifdef CONFIG_PM_SLEEP
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static int dw_mci_rockchip_suspend(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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return dw_mci_suspend(host);
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}
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static int dw_mci_rockchip_resume(struct device *dev)
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{
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struct dw_mci *host = dev_get_drvdata(dev);
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return dw_mci_resume(host);
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}
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#endif /* CONFIG_PM_SLEEP */
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static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops,
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dw_mci_rockchip_suspend,
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dw_mci_rockchip_resume);
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static struct platform_driver dw_mci_rockchip_pltfm_driver = {
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.probe = dw_mci_rockchip_probe,
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.remove = dw_mci_pltfm_remove,
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.driver = {
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.name = "dwmmc_rockchip",
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.of_match_table = dw_mci_rockchip_match,
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.pm = &dw_mci_rockchip_pmops,
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},
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};
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module_platform_driver(dw_mci_rockchip_pltfm_driver);
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MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
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MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
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MODULE_ALIAS("platform:dwmmc_rockchip");
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MODULE_LICENSE("GPL v2");
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