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![Lucas Stach](/assets/img/avatar_default.png)
The Tegra30+ SDMMC module has memcomp pads that are used to automatically find and set the correct drive strength settings to the sdmmc pads. The calibration needs to be manually kicked off when the card signal voltage is changed, after the card clock is supplied again. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Adrian Hunter <adrian.hunter@intel.com> [Ulf: Rebased to fix a trivial compile error] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
495 lines
14 KiB
C
495 lines
14 KiB
C
/*
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/gpio/consumer.h>
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#include "sdhci-pltfm.h"
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/* Tegra SDHOST controller vendor register definitions */
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#define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100
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#define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000
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#define SDHCI_CLOCK_CTRL_TAP_SHIFT 16
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#define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
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#define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3)
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#define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2)
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#define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
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#define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
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#define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
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#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
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#define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
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#define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4
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#define SDHCI_AUTO_CAL_START BIT(31)
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#define SDHCI_AUTO_CAL_ENABLE BIT(29)
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#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
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#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
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#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
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#define NVQUIRK_ENABLE_SDR50 BIT(3)
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#define NVQUIRK_ENABLE_SDR104 BIT(4)
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#define NVQUIRK_ENABLE_DDR50 BIT(5)
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#define NVQUIRK_HAS_PADCALIB BIT(6)
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struct sdhci_tegra_soc_data {
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const struct sdhci_pltfm_data *pdata;
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u32 nvquirks;
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};
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struct sdhci_tegra {
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const struct sdhci_tegra_soc_data *soc_data;
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struct gpio_desc *power_gpio;
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bool ddr_signaling;
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bool pad_calib_required;
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};
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static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
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if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
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(reg == SDHCI_HOST_VERSION))) {
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/* Erratum: Version register is invalid in HW. */
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return SDHCI_SPEC_200;
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}
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return readw(host->ioaddr + reg);
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}
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static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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switch (reg) {
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case SDHCI_TRANSFER_MODE:
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/*
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* Postpone this write, we must do it together with a
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* command write that is down below.
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*/
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pltfm_host->xfer_mode_shadow = val;
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return;
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case SDHCI_COMMAND:
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writel((val << 16) | pltfm_host->xfer_mode_shadow,
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host->ioaddr + SDHCI_TRANSFER_MODE);
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return;
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}
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writew(val, host->ioaddr + reg);
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}
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static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
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/* Seems like we're getting spurious timeout and crc errors, so
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* disable signalling of them. In case of real errors software
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* timers should take care of eventually detecting them.
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*/
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if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
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val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
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writel(val, host->ioaddr + reg);
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if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
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(reg == SDHCI_INT_ENABLE))) {
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/* Erratum: Must enable block gap interrupt detection */
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u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
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if (val & SDHCI_INT_CARD_INT)
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gap_ctrl |= 0x8;
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else
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gap_ctrl &= ~0x8;
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writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
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}
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}
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static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
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{
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return mmc_gpio_get_ro(host->mmc);
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}
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static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
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u32 misc_ctrl, clk_ctrl;
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sdhci_reset(host, mask);
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if (!(mask & SDHCI_RESET_ALL))
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return;
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misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
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/* Erratum: Enable SDHCI spec v3.00 support */
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if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
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misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
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/* Advertise UHS modes as supported by host */
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if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
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misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
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else
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misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50;
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if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
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misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
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else
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misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50;
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if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
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misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
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else
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misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104;
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sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
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clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
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clk_ctrl &= ~SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE;
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if (soc_data->nvquirks & SDHCI_MISC_CTRL_ENABLE_SDR50)
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clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
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sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
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if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
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tegra_host->pad_calib_required = true;
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tegra_host->ddr_signaling = false;
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}
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static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
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{
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u32 ctrl;
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ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
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if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
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(bus_width == MMC_BUS_WIDTH_8)) {
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ctrl &= ~SDHCI_CTRL_4BITBUS;
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ctrl |= SDHCI_CTRL_8BITBUS;
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} else {
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ctrl &= ~SDHCI_CTRL_8BITBUS;
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if (bus_width == MMC_BUS_WIDTH_4)
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ctrl |= SDHCI_CTRL_4BITBUS;
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else
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ctrl &= ~SDHCI_CTRL_4BITBUS;
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}
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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}
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static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
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{
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u32 val;
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mdelay(1);
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val = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
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val |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
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sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG);
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}
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static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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unsigned long host_clk;
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if (!clock)
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return sdhci_set_clock(host, clock);
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host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
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clk_set_rate(pltfm_host->clk, host_clk);
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host->max_clk = clk_get_rate(pltfm_host->clk);
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sdhci_set_clock(host, clock);
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if (tegra_host->pad_calib_required) {
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tegra_sdhci_pad_autocalib(host);
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tegra_host->pad_calib_required = false;
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}
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}
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static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
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unsigned timing)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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if (timing == MMC_TIMING_UHS_DDR50)
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tegra_host->ddr_signaling = true;
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return sdhci_set_uhs_signaling(host, timing);
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}
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static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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/*
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* DDR modes require the host to run at double the card frequency, so
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* the maximum rate we can support is half of the module input clock.
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*/
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return clk_round_rate(pltfm_host->clk, UINT_MAX) / 2;
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}
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static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
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{
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u32 reg;
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reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
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reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
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reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
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sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
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}
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static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
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{
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unsigned int min, max;
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/*
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* Start search for minimum tap value at 10, as smaller values are
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* may wrongly be reported as working but fail at higher speeds,
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* according to the TRM.
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*/
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min = 10;
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while (min < 255) {
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tegra_sdhci_set_tap(host, min);
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if (!mmc_send_tuning(host->mmc, opcode, NULL))
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break;
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min++;
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}
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/* Find the maximum tap value that still passes. */
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max = min + 1;
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while (max < 255) {
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tegra_sdhci_set_tap(host, max);
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if (mmc_send_tuning(host->mmc, opcode, NULL)) {
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max--;
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break;
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}
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max++;
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}
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/* The TRM states the ideal tap value is at 75% in the passing range. */
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tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
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return mmc_send_tuning(host->mmc, opcode, NULL);
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}
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static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
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const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
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if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
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tegra_host->pad_calib_required = true;
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}
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static const struct sdhci_ops tegra_sdhci_ops = {
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.get_ro = tegra_sdhci_get_ro,
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.read_w = tegra_sdhci_readw,
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.write_l = tegra_sdhci_writel,
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.set_clock = tegra_sdhci_set_clock,
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.set_bus_width = tegra_sdhci_set_bus_width,
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.reset = tegra_sdhci_reset,
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.platform_execute_tuning = tegra_sdhci_execute_tuning,
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.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
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.voltage_switch = tegra_sdhci_voltage_switch,
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.get_max_clock = tegra_sdhci_get_max_clock,
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};
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static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
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.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
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SDHCI_QUIRK_SINGLE_POWER_WRITE |
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SDHCI_QUIRK_NO_HISPD_BIT |
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SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
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SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
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.ops = &tegra_sdhci_ops,
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};
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static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
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.pdata = &sdhci_tegra20_pdata,
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.nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
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NVQUIRK_ENABLE_BLOCK_GAP_DET,
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};
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static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
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.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_SINGLE_POWER_WRITE |
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SDHCI_QUIRK_NO_HISPD_BIT |
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SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
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SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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.ops = &tegra_sdhci_ops,
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};
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static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
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.pdata = &sdhci_tegra30_pdata,
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.nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
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NVQUIRK_ENABLE_SDR50 |
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NVQUIRK_ENABLE_SDR104 |
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NVQUIRK_HAS_PADCALIB,
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};
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static const struct sdhci_ops tegra114_sdhci_ops = {
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.get_ro = tegra_sdhci_get_ro,
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.read_w = tegra_sdhci_readw,
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.write_w = tegra_sdhci_writew,
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.write_l = tegra_sdhci_writel,
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.set_clock = tegra_sdhci_set_clock,
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.set_bus_width = tegra_sdhci_set_bus_width,
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.reset = tegra_sdhci_reset,
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.platform_execute_tuning = tegra_sdhci_execute_tuning,
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.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
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.voltage_switch = tegra_sdhci_voltage_switch,
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.get_max_clock = tegra_sdhci_get_max_clock,
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};
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static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
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.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_SINGLE_POWER_WRITE |
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SDHCI_QUIRK_NO_HISPD_BIT |
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SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
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SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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.ops = &tegra114_sdhci_ops,
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};
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static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
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.pdata = &sdhci_tegra114_pdata,
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};
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static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
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.pdata = &sdhci_tegra114_pdata,
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.nvquirks = NVQUIRK_ENABLE_SDR50 |
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NVQUIRK_ENABLE_DDR50 |
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NVQUIRK_ENABLE_SDR104 |
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NVQUIRK_HAS_PADCALIB,
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};
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static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
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.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_SINGLE_POWER_WRITE |
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SDHCI_QUIRK_NO_HISPD_BIT |
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SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
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SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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.ops = &tegra114_sdhci_ops,
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};
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static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
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.pdata = &sdhci_tegra210_pdata,
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};
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static const struct of_device_id sdhci_tegra_dt_match[] = {
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{ .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
|
|
{ .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
|
|
{ .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
|
|
{ .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
|
|
{ .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
|
|
|
|
static int sdhci_tegra_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *match;
|
|
const struct sdhci_tegra_soc_data *soc_data;
|
|
struct sdhci_host *host;
|
|
struct sdhci_pltfm_host *pltfm_host;
|
|
struct sdhci_tegra *tegra_host;
|
|
struct clk *clk;
|
|
int rc;
|
|
|
|
match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
|
|
if (!match)
|
|
return -EINVAL;
|
|
soc_data = match->data;
|
|
|
|
host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
|
|
if (IS_ERR(host))
|
|
return PTR_ERR(host);
|
|
pltfm_host = sdhci_priv(host);
|
|
|
|
tegra_host = sdhci_pltfm_priv(pltfm_host);
|
|
tegra_host->ddr_signaling = false;
|
|
tegra_host->pad_calib_required = false;
|
|
tegra_host->soc_data = soc_data;
|
|
|
|
rc = mmc_of_parse(host->mmc);
|
|
if (rc)
|
|
goto err_parse_dt;
|
|
|
|
if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
|
|
host->mmc->caps |= MMC_CAP_1_8V_DDR;
|
|
|
|
tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
|
|
GPIOD_OUT_HIGH);
|
|
if (IS_ERR(tegra_host->power_gpio)) {
|
|
rc = PTR_ERR(tegra_host->power_gpio);
|
|
goto err_power_req;
|
|
}
|
|
|
|
clk = devm_clk_get(mmc_dev(host->mmc), NULL);
|
|
if (IS_ERR(clk)) {
|
|
dev_err(mmc_dev(host->mmc), "clk err\n");
|
|
rc = PTR_ERR(clk);
|
|
goto err_clk_get;
|
|
}
|
|
clk_prepare_enable(clk);
|
|
pltfm_host->clk = clk;
|
|
|
|
rc = sdhci_add_host(host);
|
|
if (rc)
|
|
goto err_add_host;
|
|
|
|
return 0;
|
|
|
|
err_add_host:
|
|
clk_disable_unprepare(pltfm_host->clk);
|
|
err_clk_get:
|
|
err_power_req:
|
|
err_parse_dt:
|
|
sdhci_pltfm_free(pdev);
|
|
return rc;
|
|
}
|
|
|
|
static struct platform_driver sdhci_tegra_driver = {
|
|
.driver = {
|
|
.name = "sdhci-tegra",
|
|
.of_match_table = sdhci_tegra_dt_match,
|
|
.pm = SDHCI_PLTFM_PMOPS,
|
|
},
|
|
.probe = sdhci_tegra_probe,
|
|
.remove = sdhci_pltfm_unregister,
|
|
};
|
|
|
|
module_platform_driver(sdhci_tegra_driver);
|
|
|
|
MODULE_DESCRIPTION("SDHCI driver for Tegra");
|
|
MODULE_AUTHOR("Google, Inc.");
|
|
MODULE_LICENSE("GPL v2");
|