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![Pan Xinhui](/assets/img/avatar_default.png)
queued_spin_lock_slowpath() should not worry about another queued_spin_lock_slowpath() running in interrupt context and changing node->count by accident, because node->count keeps the same value every time we enter/leave queued_spin_lock_slowpath(). On some architectures this_cpu_dec() will save/restore irq flags, which has high overhead. Use the much cheaper __this_cpu_dec() instead. Signed-off-by: Pan Xinhui <xinhui.pan@linux.vnet.ibm.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mike Galbraith <efault@gmx.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Waiman.Long@hpe.com Link: http://lkml.kernel.org/r/1465886247-3773-1-git-send-email-xinhui.pan@linux.vnet.ibm.com [ Rewrote changelog. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
646 lines
18 KiB
C
646 lines
18 KiB
C
/*
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* Queued spinlock
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
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* (C) Copyright 2013-2014 Red Hat, Inc.
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* (C) Copyright 2015 Intel Corp.
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* (C) Copyright 2015 Hewlett-Packard Enterprise Development LP
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*
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* Authors: Waiman Long <waiman.long@hpe.com>
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* Peter Zijlstra <peterz@infradead.org>
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*/
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#ifndef _GEN_PV_LOCK_SLOWPATH
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#include <linux/smp.h>
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#include <linux/bug.h>
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#include <linux/cpumask.h>
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#include <linux/percpu.h>
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#include <linux/hardirq.h>
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#include <linux/mutex.h>
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#include <asm/byteorder.h>
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#include <asm/qspinlock.h>
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/*
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* The basic principle of a queue-based spinlock can best be understood
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* by studying a classic queue-based spinlock implementation called the
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* MCS lock. The paper below provides a good description for this kind
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* of lock.
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*
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* http://www.cise.ufl.edu/tr/DOC/REP-1992-71.pdf
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*
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* This queued spinlock implementation is based on the MCS lock, however to make
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* it fit the 4 bytes we assume spinlock_t to be, and preserve its existing
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* API, we must modify it somehow.
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*
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* In particular; where the traditional MCS lock consists of a tail pointer
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* (8 bytes) and needs the next pointer (another 8 bytes) of its own node to
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* unlock the next pending (next->locked), we compress both these: {tail,
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* next->locked} into a single u32 value.
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*
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* Since a spinlock disables recursion of its own context and there is a limit
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* to the contexts that can nest; namely: task, softirq, hardirq, nmi. As there
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* are at most 4 nesting levels, it can be encoded by a 2-bit number. Now
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* we can encode the tail by combining the 2-bit nesting level with the cpu
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* number. With one byte for the lock value and 3 bytes for the tail, only a
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* 32-bit word is now needed. Even though we only need 1 bit for the lock,
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* we extend it to a full byte to achieve better performance for architectures
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* that support atomic byte write.
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*
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* We also change the first spinner to spin on the lock bit instead of its
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* node; whereby avoiding the need to carry a node from lock to unlock, and
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* preserving existing lock API. This also makes the unlock code simpler and
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* faster.
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*
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* N.B. The current implementation only supports architectures that allow
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* atomic operations on smaller 8-bit and 16-bit data types.
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*
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*/
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#include "mcs_spinlock.h"
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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#define MAX_NODES 8
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#else
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#define MAX_NODES 4
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#endif
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/*
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* Per-CPU queue node structures; we can never have more than 4 nested
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* contexts: task, softirq, hardirq, nmi.
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*
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* Exactly fits one 64-byte cacheline on a 64-bit architecture.
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*
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* PV doubles the storage and uses the second cacheline for PV state.
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*/
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static DEFINE_PER_CPU_ALIGNED(struct mcs_spinlock, mcs_nodes[MAX_NODES]);
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/*
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* We must be able to distinguish between no-tail and the tail at 0:0,
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* therefore increment the cpu number by one.
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*/
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static inline __pure u32 encode_tail(int cpu, int idx)
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{
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u32 tail;
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#ifdef CONFIG_DEBUG_SPINLOCK
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BUG_ON(idx > 3);
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#endif
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tail = (cpu + 1) << _Q_TAIL_CPU_OFFSET;
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tail |= idx << _Q_TAIL_IDX_OFFSET; /* assume < 4 */
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return tail;
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}
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static inline __pure struct mcs_spinlock *decode_tail(u32 tail)
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{
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int cpu = (tail >> _Q_TAIL_CPU_OFFSET) - 1;
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int idx = (tail & _Q_TAIL_IDX_MASK) >> _Q_TAIL_IDX_OFFSET;
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return per_cpu_ptr(&mcs_nodes[idx], cpu);
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}
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#define _Q_LOCKED_PENDING_MASK (_Q_LOCKED_MASK | _Q_PENDING_MASK)
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/*
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* By using the whole 2nd least significant byte for the pending bit, we
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* can allow better optimization of the lock acquisition for the pending
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* bit holder.
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*
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* This internal structure is also used by the set_locked function which
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* is not restricted to _Q_PENDING_BITS == 8.
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*/
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struct __qspinlock {
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union {
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atomic_t val;
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#ifdef __LITTLE_ENDIAN
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struct {
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u8 locked;
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u8 pending;
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};
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struct {
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u16 locked_pending;
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u16 tail;
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};
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#else
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struct {
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u16 tail;
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u16 locked_pending;
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};
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struct {
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u8 reserved[2];
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u8 pending;
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u8 locked;
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};
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#endif
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};
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};
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#if _Q_PENDING_BITS == 8
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/**
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* clear_pending_set_locked - take ownership and clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,0 -> *,0,1
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*
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* Lock stealing is not allowed if this function is used.
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*/
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static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
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{
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struct __qspinlock *l = (void *)lock;
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WRITE_ONCE(l->locked_pending, _Q_LOCKED_VAL);
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}
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/*
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* xchg_tail - Put in the new queue tail code word & retrieve previous one
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* @lock : Pointer to queued spinlock structure
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* @tail : The new queue tail code word
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* Return: The previous queue tail code word
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*
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* xchg(lock, tail)
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*
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* p,*,* -> n,*,* ; prev = xchg(lock, node)
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*/
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static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
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{
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struct __qspinlock *l = (void *)lock;
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/*
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* Use release semantics to make sure that the MCS node is properly
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* initialized before changing the tail code.
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*/
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return (u32)xchg_release(&l->tail,
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tail >> _Q_TAIL_OFFSET) << _Q_TAIL_OFFSET;
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}
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#else /* _Q_PENDING_BITS == 8 */
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/**
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* clear_pending_set_locked - take ownership and clear the pending bit.
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* @lock: Pointer to queued spinlock structure
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*
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* *,1,0 -> *,0,1
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*/
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static __always_inline void clear_pending_set_locked(struct qspinlock *lock)
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{
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atomic_add(-_Q_PENDING_VAL + _Q_LOCKED_VAL, &lock->val);
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}
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/**
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* xchg_tail - Put in the new queue tail code word & retrieve previous one
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* @lock : Pointer to queued spinlock structure
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* @tail : The new queue tail code word
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* Return: The previous queue tail code word
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*
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* xchg(lock, tail)
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*
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* p,*,* -> n,*,* ; prev = xchg(lock, node)
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*/
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static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail)
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{
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u32 old, new, val = atomic_read(&lock->val);
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for (;;) {
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new = (val & _Q_LOCKED_PENDING_MASK) | tail;
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/*
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* Use release semantics to make sure that the MCS node is
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* properly initialized before changing the tail code.
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*/
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old = atomic_cmpxchg_release(&lock->val, val, new);
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if (old == val)
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break;
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val = old;
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}
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return old;
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}
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#endif /* _Q_PENDING_BITS == 8 */
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/**
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* set_locked - Set the lock bit and own the lock
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* @lock: Pointer to queued spinlock structure
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*
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* *,*,0 -> *,0,1
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*/
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static __always_inline void set_locked(struct qspinlock *lock)
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{
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struct __qspinlock *l = (void *)lock;
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WRITE_ONCE(l->locked, _Q_LOCKED_VAL);
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}
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/*
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* Generate the native code for queued_spin_unlock_slowpath(); provide NOPs for
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* all the PV callbacks.
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*/
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static __always_inline void __pv_init_node(struct mcs_spinlock *node) { }
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static __always_inline void __pv_wait_node(struct mcs_spinlock *node,
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struct mcs_spinlock *prev) { }
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static __always_inline void __pv_kick_node(struct qspinlock *lock,
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struct mcs_spinlock *node) { }
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static __always_inline u32 __pv_wait_head_or_lock(struct qspinlock *lock,
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struct mcs_spinlock *node)
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{ return 0; }
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#define pv_enabled() false
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#define pv_init_node __pv_init_node
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#define pv_wait_node __pv_wait_node
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#define pv_kick_node __pv_kick_node
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#define pv_wait_head_or_lock __pv_wait_head_or_lock
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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#define queued_spin_lock_slowpath native_queued_spin_lock_slowpath
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#endif
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/*
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* Various notes on spin_is_locked() and spin_unlock_wait(), which are
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* 'interesting' functions:
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*
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* PROBLEM: some architectures have an interesting issue with atomic ACQUIRE
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* operations in that the ACQUIRE applies to the LOAD _not_ the STORE (ARM64,
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* PPC). Also qspinlock has a similar issue per construction, the setting of
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* the locked byte can be unordered acquiring the lock proper.
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*
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* This gets to be 'interesting' in the following cases, where the /should/s
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* end up false because of this issue.
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*
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*
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* CASE 1:
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*
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* So the spin_is_locked() correctness issue comes from something like:
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*
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* CPU0 CPU1
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*
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* global_lock(); local_lock(i)
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* spin_lock(&G) spin_lock(&L[i])
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* for (i) if (!spin_is_locked(&G)) {
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* spin_unlock_wait(&L[i]); smp_acquire__after_ctrl_dep();
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* return;
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* }
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* // deal with fail
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*
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* Where it is important CPU1 sees G locked or CPU0 sees L[i] locked such
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* that there is exclusion between the two critical sections.
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*
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* The load from spin_is_locked(&G) /should/ be constrained by the ACQUIRE from
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* spin_lock(&L[i]), and similarly the load(s) from spin_unlock_wait(&L[i])
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* /should/ be constrained by the ACQUIRE from spin_lock(&G).
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*
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* Similarly, later stuff is constrained by the ACQUIRE from CTRL+RMB.
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*
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*
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* CASE 2:
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*
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* For spin_unlock_wait() there is a second correctness issue, namely:
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*
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* CPU0 CPU1
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*
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* flag = set;
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* smp_mb(); spin_lock(&l)
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* spin_unlock_wait(&l); if (!flag)
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* // add to lockless list
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* spin_unlock(&l);
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* // iterate lockless list
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*
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* Which wants to ensure that CPU1 will stop adding bits to the list and CPU0
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* will observe the last entry on the list (if spin_unlock_wait() had ACQUIRE
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* semantics etc..)
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*
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* Where flag /should/ be ordered against the locked store of l.
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*/
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/*
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* queued_spin_lock_slowpath() can (load-)ACQUIRE the lock before
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* issuing an _unordered_ store to set _Q_LOCKED_VAL.
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*
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* This means that the store can be delayed, but no later than the
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* store-release from the unlock. This means that simply observing
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* _Q_LOCKED_VAL is not sufficient to determine if the lock is acquired.
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*
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* There are two paths that can issue the unordered store:
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*
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* (1) clear_pending_set_locked(): *,1,0 -> *,0,1
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*
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* (2) set_locked(): t,0,0 -> t,0,1 ; t != 0
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* atomic_cmpxchg_relaxed(): t,0,0 -> 0,0,1
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*
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* However, in both cases we have other !0 state we've set before to queue
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* ourseves:
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*
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* For (1) we have the atomic_cmpxchg_acquire() that set _Q_PENDING_VAL, our
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* load is constrained by that ACQUIRE to not pass before that, and thus must
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* observe the store.
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*
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* For (2) we have a more intersting scenario. We enqueue ourselves using
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* xchg_tail(), which ends up being a RELEASE. This in itself is not
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* sufficient, however that is followed by an smp_cond_acquire() on the same
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* word, giving a RELEASE->ACQUIRE ordering. This again constrains our load and
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* guarantees we must observe that store.
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*
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* Therefore both cases have other !0 state that is observable before the
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* unordered locked byte store comes through. This means we can use that to
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* wait for the lock store, and then wait for an unlock.
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*/
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#ifndef queued_spin_unlock_wait
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void queued_spin_unlock_wait(struct qspinlock *lock)
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{
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u32 val;
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for (;;) {
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val = atomic_read(&lock->val);
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if (!val) /* not locked, we're done */
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goto done;
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if (val & _Q_LOCKED_MASK) /* locked, go wait for unlock */
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break;
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/* not locked, but pending, wait until we observe the lock */
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cpu_relax();
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}
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/* any unlock is good */
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while (atomic_read(&lock->val) & _Q_LOCKED_MASK)
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cpu_relax();
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done:
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smp_acquire__after_ctrl_dep();
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}
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EXPORT_SYMBOL(queued_spin_unlock_wait);
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#endif
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#endif /* _GEN_PV_LOCK_SLOWPATH */
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/**
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* queued_spin_lock_slowpath - acquire the queued spinlock
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* @lock: Pointer to queued spinlock structure
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* @val: Current value of the queued spinlock 32-bit word
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*
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* (queue tail, pending bit, lock value)
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*
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* fast : slow : unlock
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* : :
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* uncontended (0,0,0) -:--> (0,0,1) ------------------------------:--> (*,*,0)
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* : | ^--------.------. / :
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* : v \ \ | :
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* pending : (0,1,1) +--> (0,1,0) \ | :
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* : | ^--' | | :
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* : v | | :
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* uncontended : (n,x,y) +--> (n,0,0) --' | :
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* queue : | ^--' | :
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* : v | :
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* contended : (*,x,y) +--> (*,0,0) ---> (*,0,1) -' :
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* queue : ^--' :
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*/
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void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val)
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{
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struct mcs_spinlock *prev, *next, *node;
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u32 new, old, tail;
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int idx;
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BUILD_BUG_ON(CONFIG_NR_CPUS >= (1U << _Q_TAIL_CPU_BITS));
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if (pv_enabled())
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goto queue;
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if (virt_spin_lock(lock))
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return;
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/*
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* wait for in-progress pending->locked hand-overs
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*
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* 0,1,0 -> 0,0,1
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*/
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if (val == _Q_PENDING_VAL) {
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while ((val = atomic_read(&lock->val)) == _Q_PENDING_VAL)
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cpu_relax();
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}
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/*
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* trylock || pending
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*
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* 0,0,0 -> 0,0,1 ; trylock
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* 0,0,1 -> 0,1,1 ; pending
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*/
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for (;;) {
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/*
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* If we observe any contention; queue.
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*/
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if (val & ~_Q_LOCKED_MASK)
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goto queue;
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new = _Q_LOCKED_VAL;
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if (val == new)
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new |= _Q_PENDING_VAL;
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/*
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* Acquire semantic is required here as the function may
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* return immediately if the lock was free.
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*/
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old = atomic_cmpxchg_acquire(&lock->val, val, new);
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if (old == val)
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break;
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val = old;
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}
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/*
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* we won the trylock
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*/
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if (new == _Q_LOCKED_VAL)
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return;
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/*
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* we're pending, wait for the owner to go away.
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*
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* *,1,1 -> *,1,0
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*
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* this wait loop must be a load-acquire such that we match the
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* store-release that clears the locked bit and create lock
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* sequentiality; this is because not all clear_pending_set_locked()
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* implementations imply full barriers.
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*/
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smp_cond_load_acquire(&lock->val.counter, !(VAL & _Q_LOCKED_MASK));
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/*
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* take ownership and clear the pending bit.
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*
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* *,1,0 -> *,0,1
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*/
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clear_pending_set_locked(lock);
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return;
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/*
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* End of pending bit optimistic spinning and beginning of MCS
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* queuing.
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*/
|
|
queue:
|
|
node = this_cpu_ptr(&mcs_nodes[0]);
|
|
idx = node->count++;
|
|
tail = encode_tail(smp_processor_id(), idx);
|
|
|
|
node += idx;
|
|
node->locked = 0;
|
|
node->next = NULL;
|
|
pv_init_node(node);
|
|
|
|
/*
|
|
* We touched a (possibly) cold cacheline in the per-cpu queue node;
|
|
* attempt the trylock once more in the hope someone let go while we
|
|
* weren't watching.
|
|
*/
|
|
if (queued_spin_trylock(lock))
|
|
goto release;
|
|
|
|
/*
|
|
* We have already touched the queueing cacheline; don't bother with
|
|
* pending stuff.
|
|
*
|
|
* p,*,* -> n,*,*
|
|
*
|
|
* RELEASE, such that the stores to @node must be complete.
|
|
*/
|
|
old = xchg_tail(lock, tail);
|
|
next = NULL;
|
|
|
|
/*
|
|
* if there was a previous node; link it and wait until reaching the
|
|
* head of the waitqueue.
|
|
*/
|
|
if (old & _Q_TAIL_MASK) {
|
|
prev = decode_tail(old);
|
|
/*
|
|
* The above xchg_tail() is also a load of @lock which generates,
|
|
* through decode_tail(), a pointer.
|
|
*
|
|
* The address dependency matches the RELEASE of xchg_tail()
|
|
* such that the access to @prev must happen after.
|
|
*/
|
|
smp_read_barrier_depends();
|
|
|
|
WRITE_ONCE(prev->next, node);
|
|
|
|
pv_wait_node(node, prev);
|
|
arch_mcs_spin_lock_contended(&node->locked);
|
|
|
|
/*
|
|
* While waiting for the MCS lock, the next pointer may have
|
|
* been set by another lock waiter. We optimistically load
|
|
* the next pointer & prefetch the cacheline for writing
|
|
* to reduce latency in the upcoming MCS unlock operation.
|
|
*/
|
|
next = READ_ONCE(node->next);
|
|
if (next)
|
|
prefetchw(next);
|
|
}
|
|
|
|
/*
|
|
* we're at the head of the waitqueue, wait for the owner & pending to
|
|
* go away.
|
|
*
|
|
* *,x,y -> *,0,0
|
|
*
|
|
* this wait loop must use a load-acquire such that we match the
|
|
* store-release that clears the locked bit and create lock
|
|
* sequentiality; this is because the set_locked() function below
|
|
* does not imply a full barrier.
|
|
*
|
|
* The PV pv_wait_head_or_lock function, if active, will acquire
|
|
* the lock and return a non-zero value. So we have to skip the
|
|
* smp_cond_load_acquire() call. As the next PV queue head hasn't been
|
|
* designated yet, there is no way for the locked value to become
|
|
* _Q_SLOW_VAL. So both the set_locked() and the
|
|
* atomic_cmpxchg_relaxed() calls will be safe.
|
|
*
|
|
* If PV isn't active, 0 will be returned instead.
|
|
*
|
|
*/
|
|
if ((val = pv_wait_head_or_lock(lock, node)))
|
|
goto locked;
|
|
|
|
val = smp_cond_load_acquire(&lock->val.counter, !(VAL & _Q_LOCKED_PENDING_MASK));
|
|
|
|
locked:
|
|
/*
|
|
* claim the lock:
|
|
*
|
|
* n,0,0 -> 0,0,1 : lock, uncontended
|
|
* *,0,0 -> *,0,1 : lock, contended
|
|
*
|
|
* If the queue head is the only one in the queue (lock value == tail),
|
|
* clear the tail code and grab the lock. Otherwise, we only need
|
|
* to grab the lock.
|
|
*/
|
|
for (;;) {
|
|
/* In the PV case we might already have _Q_LOCKED_VAL set */
|
|
if ((val & _Q_TAIL_MASK) != tail) {
|
|
set_locked(lock);
|
|
break;
|
|
}
|
|
/*
|
|
* The smp_cond_load_acquire() call above has provided the
|
|
* necessary acquire semantics required for locking. At most
|
|
* two iterations of this loop may be ran.
|
|
*/
|
|
old = atomic_cmpxchg_relaxed(&lock->val, val, _Q_LOCKED_VAL);
|
|
if (old == val)
|
|
goto release; /* No contention */
|
|
|
|
val = old;
|
|
}
|
|
|
|
/*
|
|
* contended path; wait for next if not observed yet, release.
|
|
*/
|
|
if (!next) {
|
|
while (!(next = READ_ONCE(node->next)))
|
|
cpu_relax();
|
|
}
|
|
|
|
arch_mcs_spin_unlock_contended(&next->locked);
|
|
pv_kick_node(lock, next);
|
|
|
|
release:
|
|
/*
|
|
* release the node
|
|
*/
|
|
__this_cpu_dec(mcs_nodes[0].count);
|
|
}
|
|
EXPORT_SYMBOL(queued_spin_lock_slowpath);
|
|
|
|
/*
|
|
* Generate the paravirt code for queued_spin_unlock_slowpath().
|
|
*/
|
|
#if !defined(_GEN_PV_LOCK_SLOWPATH) && defined(CONFIG_PARAVIRT_SPINLOCKS)
|
|
#define _GEN_PV_LOCK_SLOWPATH
|
|
|
|
#undef pv_enabled
|
|
#define pv_enabled() true
|
|
|
|
#undef pv_init_node
|
|
#undef pv_wait_node
|
|
#undef pv_kick_node
|
|
#undef pv_wait_head_or_lock
|
|
|
|
#undef queued_spin_lock_slowpath
|
|
#define queued_spin_lock_slowpath __pv_queued_spin_lock_slowpath
|
|
|
|
#include "qspinlock_paravirt.h"
|
|
#include "qspinlock.c"
|
|
|
|
#endif
|