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7a29a86943
This patchset adds the infrastructure for registering and managing the core clocks found on Amlogic MesonX SoCs. In particular: - PLLs - CPU clock - Fixed rate clocks, fixed factor clocks, ... Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
25 lines
508 B
C
25 lines
508 B
C
/*
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* Meson8b clock tree IDs
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*/
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#ifndef __MESON8B_CLKC_H
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#define __MESON8B_CLKC_H
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#define CLKID_UNUSED 0
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#define CLKID_XTAL 1
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#define CLKID_PLL_FIXED 2
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#define CLKID_PLL_VID 3
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#define CLKID_PLL_SYS 4
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#define CLKID_FCLK_DIV2 5
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#define CLKID_FCLK_DIV3 6
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#define CLKID_FCLK_DIV4 7
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#define CLKID_FCLK_DIV5 8
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#define CLKID_FCLK_DIV7 9
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#define CLKID_CLK81 10
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#define CLKID_MALI 11
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#define CLKID_CPUCLK 12
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#define CLKID_ZERO 13
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#define CLK_NR_CLKS (CLKID_ZERO + 1)
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#endif /* __MESON8B_CLKC_H */
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