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a97e384ba7
This makes it possible to select CONFIG_SND_MMP_SOC_SSPA directly, as opposed to via CONFIG_SND_MMP_SOC, and for the driver to bind to a device tree node. That makes the driver useful on Device Tree based systems, with audio-graph-card or simple-card. The aforementioned card drivers control the master clock themselves and don't call the set_dai_sysclk() or set_dai_pll(), thus the respective handlers don't serve any purpose anymore. Instead, they return early and the hw_params() handler sets the appropriate bitclk itself. The register range is split into two -- for the RX block and for the TX block. On a MMP2 there are two pairs of them; the first one has the clock controller in the middle, while the second just has a hole: 0xd42a0c00 - 0xd42a0c30 RX1 0xd42a0c30 - 0xd42a0c40 Clocks 0xd42a0c80 - 0xd42a0cb0 TX1 0xd42a0d00 - 0xd42a0d30 RX2 0xd42a0d80 - 0xd42a0cb0 TX2 For this reason, mmp_sspa_write_reg() and mmp_sspa_read_reg() are replaced with direct calls to I/O routines. Tested on a MMP2-based OLPC XO-1.75 laptop with rt5631 coded, mmp_tdma DMA engine and MMP2 clock controller glued together with audio-graph-card. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20200511210134.1224532-12-lkundrak@v3.sk Signed-off-by: Mark Brown <broonie@kernel.org>
70 lines
2.4 KiB
C
70 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* linux/sound/soc/pxa/mmp-sspa.h
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*
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* Copyright (C) 2011 Marvell International Ltd.
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*/
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#ifndef _MMP_SSPA_H
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#define _MMP_SSPA_H
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/*
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* SSPA Registers
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*/
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#define SSPA_D (0x00)
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#define SSPA_ID (0x04)
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#define SSPA_CTL (0x08)
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#define SSPA_SP (0x0c)
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#define SSPA_FIFO_UL (0x10)
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#define SSPA_INT_MASK (0x14)
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#define SSPA_C (0x18)
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#define SSPA_FIFO_NOFS (0x1c)
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#define SSPA_FIFO_SIZE (0x20)
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/* SSPA Control Register */
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#define SSPA_CTL_XPH (1 << 31) /* Read Phase */
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#define SSPA_CTL_XFIG (1 << 15) /* Transmit Zeros when FIFO Empty */
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#define SSPA_CTL_JST (1 << 3) /* Audio Sample Justification */
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#define SSPA_CTL_XFRLEN2_MASK (7 << 24)
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#define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */
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#define SSPA_CTL_XWDLEN2_MASK (7 << 21)
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#define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */
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#define SSPA_CTL_XDATDLY(x) ((x) << 19) /* Transmit Data Delay */
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#define SSPA_CTL_XSSZ2_MASK (7 << 16)
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#define SSPA_CTL_XSSZ2(x) ((x) << 16) /* Transmit Sample Audio Size */
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#define SSPA_CTL_XFRLEN1_MASK (7 << 8)
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#define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */
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#define SSPA_CTL_XWDLEN1_MASK (7 << 5)
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#define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */
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#define SSPA_CTL_XSSZ1_MASK (7 << 0)
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#define SSPA_CTL_XSSZ1(x) ((x) << 0) /* XSSZ1 */
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#define SSPA_CTL_8_BITS (0x0) /* Sample Size */
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#define SSPA_CTL_12_BITS (0x1)
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#define SSPA_CTL_16_BITS (0x2)
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#define SSPA_CTL_20_BITS (0x3)
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#define SSPA_CTL_24_BITS (0x4)
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#define SSPA_CTL_32_BITS (0x5)
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/* SSPA Serial Port Register */
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#define SSPA_SP_WEN (1 << 31) /* Write Configuration Enable */
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#define SSPA_SP_MSL (1 << 18) /* Master Slave Configuration */
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#define SSPA_SP_CLKP (1 << 17) /* CLKP Polarity Clock Edge Select */
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#define SSPA_SP_FSP (1 << 16) /* FSP Polarity Clock Edge Select */
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#define SSPA_SP_FFLUSH (1 << 2) /* FIFO Flush */
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#define SSPA_SP_S_RST (1 << 1) /* Active High Reset Signal */
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#define SSPA_SP_S_EN (1 << 0) /* Serial Clock Domain Enable */
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#define SSPA_SP_FWID_MASK (0x3f << 20)
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#define SSPA_SP_FWID(x) ((x) << 20) /* Frame-Sync Width */
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#define SSPA_TXSP_FPER_MASK (0x3f << 4)
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#define SSPA_TXSP_FPER(x) ((x) << 4) /* Frame-Sync Active */
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/* sspa clock sources */
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#define MMP_SSPA_CLK_PLL 0
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#define MMP_SSPA_CLK_VCXO 1
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#define MMP_SSPA_CLK_AUDIO 3
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/* sspa pll id */
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#define MMP_SYSCLK 0
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#define MMP_SSPA_CLK 1
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#endif /* _MMP_SSPA_H */
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