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linux-stable/arch/riscv/kernel
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Mingzheng Xing ca09f772cc
riscv: Handle zicsr/zifencei issue between gcc and binutils 
Binutils-2.38 and GCC-12.1.0 bumped[0][1] the default ISA spec to the newer
20191213 version which moves some instructions from the I extension to the
Zicsr and Zifencei extensions. So if one of the binutils and GCC exceeds
that version, we should explicitly specifying Zicsr and Zifencei via -march
to cope with the new changes. but this only occurs when binutils >= 2.36
and GCC >= 11.1.0. It's a different story when binutils < 2.36.

binutils-2.36 supports the Zifencei extension[2] and splits Zifencei and
Zicsr from I[3]. GCC-11.1.0 is particular[4] because it add support Zicsr
and Zifencei extension for -march. binutils-2.35 does not support the
Zifencei extension, and does not need to specify Zicsr and Zifencei when
working with GCC >= 12.1.0.

To make our lives easier, let's relax the check to binutils >= 2.36 in
CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI. For the other two cases,
where clang < 17 or GCC < 11.1.0, we will deal with them in
CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC.

For more information, please refer to:
commit 6df2a016c0 ("riscv: fix build with binutils 2.38")
commit e89c2e815e ("riscv: Handle zicsr/zifencei issues between clang and binutils")

Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc [0]
Link: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=98416dbb0a62579d4a7a4a76bab51b5b52fec2cd [1]
Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=5a1b31e1e1cee6e9f1c92abff59cdcfff0dddf30 [2]
Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=729a53530e86972d1143553a415db34e6e01d5d2 [3]
Link: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=b03be74bad08c382da47e048007a78fa3fb4ef49 [4]
Link: https://lore.kernel.org/all/20230308220842.1231003-1-conor@kernel.org
Link: https://lore.kernel.org/all/20230223220546.52879-1-conor@kernel.org
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Guo Ren <guoren@kernel.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
Link: https://lore.kernel.org/r/20230809165648.21071-1-xingmingzheng@iscas.ac.cn
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-08-16 07:39:38 -07:00
..
compat_vdso riscv: Handle zicsr/zifencei issue between gcc and binutils 2023-08-16 07:39:38 -07:00
pi riscv: Fix orphan section warnings caused by kernel/pi 2023-05-09 18:20:23 -07:00
probes RISC-V Patches for the 6.5 Merge Window, Part 1 2023-06-30 09:37:26 -07:00
vdso riscv: replace deprecated scall with ecall 2023-06-20 09:02:09 -07:00
.gitignore
acpi.c RISC-V: ACPI: Fix acpi_os_ioremap to return iomem address 2023-08-02 13:49:43 -07:00
alternative.c RISC-V: hwprobe: Remove __init on probe_vendor_features() 2023-04-25 21:58:42 -07:00
asm-offsets.c RISC-V: Add arch functions to support hibernation/suspend-to-disk 2023-04-29 11:25:13 -07:00
cacheinfo.c RISC-V Patches for the 6.4 Merge Window, Part 1 2023-04-28 16:55:39 -07:00
compat_signal.c
compat_syscall_table.c
cpu-hotplug.c riscv: Switch to hotplug core state synchronization 2023-05-15 13:44:59 +02:00
cpu.c riscv: Fix CPU feature detection with SMP disabled 2023-08-08 15:28:25 -07:00
cpu_ops.c RISC-V: Align SBI probe implementation with spec 2023-04-29 13:04:50 -07:00
cpu_ops_sbi.c riscv: cpu_ops_sbi: Add 64bit hartid support on RV64 2022-07-19 16:38:58 -07:00
cpu_ops_spinwait.c RISC-V: cpu_ops_spinwait.c should include head.h 2022-08-11 13:24:16 -07:00
cpufeature.c RISC-V: Don't include Zicsr or Zifencei in I from ACPI 2023-07-12 10:04:40 -07:00
crash_core.c riscv: Export va_kernel_pa_offset in vmcoreinfo 2023-08-02 13:50:31 -07:00
crash_dump.c
crash_save_regs.S RISC-V: Fixup get incorrect user mode PC for kernel mode regs 2022-08-11 08:54:40 -07:00
efi-header.S riscv: Prepare EFI header for relocatable kernels 2023-04-19 07:46:28 -07:00
efi.c efi: Discover BTI support in runtime services regions 2023-02-04 09:19:02 +01:00
elf_kexec.c riscv/kexec: load initrd high in available memory 2023-08-04 10:27:44 -07:00
entry.S riscv: replace deprecated scall with ecall 2023-06-20 09:02:09 -07:00
fpu.S
ftrace.c RISC-V: Don't check text_mutex during stop_machine 2023-03-09 14:58:51 -08:00
head.h riscv: entry: Convert to generic entry 2023-03-23 08:47:00 -07:00
head.S riscv: prevent stack corruption by reserving task_pt_regs(p) early 2023-06-08 07:16:49 -07:00
hibernate-asm.S riscv: hibernation: Remove duplicate call of suspend_restore_csrs 2023-06-19 09:27:57 -07:00
hibernate.c riscv: hibernate: remove WARN_ON in save_processor_state 2023-06-23 10:06:22 -07:00
image-vars.h riscv: Fix EFI stub usage of KASAN instrumented strcmp function 2023-04-19 07:24:52 -07:00
irq.c riscv: stack: Fixup independent softirq stack for CONFIG_FRAME_POINTER=n 2023-08-16 07:26:29 -07:00
jump_label.c jump_label: make initial NOP patching the special case 2022-06-24 09:48:55 +02:00
kexec_relocate.S
kgdb.c RISC-V: rename parse_asm.h to insn.h 2022-12-29 06:59:47 -08:00
machine_kexec.c riscv: kexec: Fixup crash_smp_send_stop without multi cores 2022-11-29 21:50:59 -08:00
machine_kexec_file.c
Makefile RISC-V Patches for the 6.5 Merge Window, Part 1 2023-06-30 09:37:26 -07:00
mcount-dyn.S riscv: entry: Consolidate general regs saving/restoring 2023-03-23 08:47:03 -07:00
mcount.S riscv: ftrace: Enable HAVE_FUNCTION_GRAPH_RETVAL 2023-06-22 10:39:56 -04:00
module-sections.c
module.c riscv: module: Add ADD16 and SUB16 rela types 2023-01-31 23:29:40 -08:00
patch.c RISC-V: Don't check text_mutex during stop_machine 2023-03-09 14:58:51 -08:00
perf_callchain.c
perf_regs.c
process.c riscv: Add prctl controls for userspace vector management 2023-06-08 07:16:53 -07:00
ptrace.c riscv: Add ptrace vector support 2023-06-08 07:16:45 -07:00
reset.c
riscv_ksyms.c RISC-V: add infrastructure to allow different str* implementations 2023-01-31 11:43:23 -08:00
sbi-ipi.c RISC-V: Allow marking IPIs as suitable for remote FENCEs 2023-04-08 11:26:24 +01:00
sbi.c RISC-V: Align SBI probe implementation with spec 2023-04-29 13:04:50 -07:00
setup.c Merge patch series "riscv: Add vector ISA support" 2023-06-08 07:17:09 -07:00
signal.c riscv: signal: validate altstack to reflect Vector 2023-06-08 07:16:48 -07:00
smp.c riscv: Fix CPU feature detection with SMP disabled 2023-08-08 15:28:25 -07:00
smpboot.c risc-v: Fix order of IPI enablement vs RCU startup 2023-07-05 07:24:38 -07:00
soc.c
stacktrace.c riscv: Use READ_ONCE_NOCHECK in imprecise unwinding stack mode 2023-03-09 14:50:35 -08:00
suspend.c RISC-V: Change suspend_save_csrs and suspend_restore_csrs to public function 2023-04-29 11:25:10 -07:00
suspend_entry.S RISC-V: Factor out common code of __cpu_resume_enter() 2023-04-29 11:25:11 -07:00
sys_riscv.c Merge patch series "RISC-V: Export Zba, Zbb to usermode via hwprobe" 2023-06-19 14:34:40 -07:00
syscall_table.c
time.c RISC-V: time.c: Add ACPI support for time_init() 2023-06-01 08:45:13 -07:00
traps.c riscv: stack: Fixup independent irq stack for CONFIG_FRAME_POINTER=n 2023-08-16 07:26:28 -07:00
traps_misaligned.c riscv: traps_misaligned: do not duplicate stringify 2022-08-11 08:56:53 -07:00
vdso.c riscv: vdso: include vdso/vsyscall.h for vdso_data 2023-07-04 07:54:41 -07:00
vector.c riscv: vector: clear V-reg in the first-use trap 2023-07-01 07:38:21 -07:00
vmlinux-xip.lds.S riscv: vmlinux-xip.lds.S: remove .alternative section 2023-06-25 16:24:03 -07:00
vmlinux.lds.S riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION 2023-06-25 16:24:05 -07:00