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To support SNP, IOMMU needs to be enabled, and prohibits IOMMU configurations where DTE[Mode]=0, which means it cannot be supported with IOMMU passthrough domain (a.k.a IOMMU_DOMAIN_IDENTITY), and when AMD IOMMU driver is configured to not use the IOMMU host (v1) page table. Otherwise, RMP table initialization could cause the system to crash. The request to enable SNP support in IOMMU must be done before PCI initialization state of the IOMMU driver because enabling SNP affects how IOMMU driver sets up IOMMU data structures (i.e. DTE). Unlike other IOMMU features, SNP feature does not have an enable bit in the IOMMU control register. Instead, the IOMMU driver introduces an amd_iommu_snp_en variable to track enabling state of SNP. Introduce amd_iommu_snp_enable() for other drivers to request enabling the SNP support in IOMMU, which checks all prerequisites and determines if the feature can be safely enabled. Please see the IOMMU spec section 2.12 for further details. Reviewed-by: Robin Murphy <robin.murphy@arm.com> Co-developed-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Link: https://lore.kernel.org/r/20220713225651.20758-7-suravee.suthikulpanit@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
213 lines
6.2 KiB
C
213 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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* Leo Duran <leo.duran@amd.com>
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*/
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#ifndef _ASM_X86_AMD_IOMMU_H
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#define _ASM_X86_AMD_IOMMU_H
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#include <linux/types.h>
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struct amd_iommu;
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/*
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* This is mainly used to communicate information back-and-forth
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* between SVM and IOMMU for setting up and tearing down posted
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* interrupt
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*/
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struct amd_iommu_pi_data {
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u32 ga_tag;
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u32 prev_ga_tag;
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u64 base;
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bool is_guest_mode;
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struct vcpu_data *vcpu_data;
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void *ir_data;
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};
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#ifdef CONFIG_AMD_IOMMU
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struct task_struct;
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struct pci_dev;
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extern int amd_iommu_detect(void);
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extern int amd_iommu_init_hardware(void);
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/**
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* amd_iommu_init_device() - Init device for use with IOMMUv2 driver
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* @pdev: The PCI device to initialize
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* @pasids: Number of PASIDs to support for this device
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*
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* This function does all setup for the device pdev so that it can be
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* used with IOMMUv2.
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* Returns 0 on success or negative value on error.
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*/
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extern int amd_iommu_init_device(struct pci_dev *pdev, int pasids);
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/**
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* amd_iommu_free_device() - Free all IOMMUv2 related device resources
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* and disable IOMMUv2 usage for this device
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* @pdev: The PCI device to disable IOMMUv2 usage for'
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*/
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extern void amd_iommu_free_device(struct pci_dev *pdev);
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/**
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* amd_iommu_bind_pasid() - Bind a given task to a PASID on a device
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* @pdev: The PCI device to bind the task to
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* @pasid: The PASID on the device the task should be bound to
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* @task: the task to bind
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*
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* The function returns 0 on success or a negative value on error.
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*/
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extern int amd_iommu_bind_pasid(struct pci_dev *pdev, u32 pasid,
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struct task_struct *task);
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/**
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* amd_iommu_unbind_pasid() - Unbind a PASID from its task on
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* a device
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* @pdev: The device of the PASID
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* @pasid: The PASID to unbind
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*
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* When this function returns the device is no longer using the PASID
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* and the PASID is no longer bound to its task.
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*/
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extern void amd_iommu_unbind_pasid(struct pci_dev *pdev, u32 pasid);
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/**
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* amd_iommu_set_invalid_ppr_cb() - Register a call-back for failed
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* PRI requests
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* @pdev: The PCI device the call-back should be registered for
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* @cb: The call-back function
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*
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* The IOMMUv2 driver invokes this call-back when it is unable to
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* successfully handle a PRI request. The device driver can then decide
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* which PRI response the device should see. Possible return values for
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* the call-back are:
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*
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* - AMD_IOMMU_INV_PRI_RSP_SUCCESS - Send SUCCESS back to the device
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* - AMD_IOMMU_INV_PRI_RSP_INVALID - Send INVALID back to the device
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* - AMD_IOMMU_INV_PRI_RSP_FAIL - Send Failure back to the device,
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* the device is required to disable
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* PRI when it receives this response
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*
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* The function returns 0 on success or negative value on error.
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*/
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#define AMD_IOMMU_INV_PRI_RSP_SUCCESS 0
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#define AMD_IOMMU_INV_PRI_RSP_INVALID 1
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#define AMD_IOMMU_INV_PRI_RSP_FAIL 2
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typedef int (*amd_iommu_invalid_ppr_cb)(struct pci_dev *pdev,
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u32 pasid,
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unsigned long address,
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u16);
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extern int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
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amd_iommu_invalid_ppr_cb cb);
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#define PPR_FAULT_EXEC (1 << 1)
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#define PPR_FAULT_READ (1 << 2)
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#define PPR_FAULT_WRITE (1 << 5)
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#define PPR_FAULT_USER (1 << 6)
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#define PPR_FAULT_RSVD (1 << 7)
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#define PPR_FAULT_GN (1 << 8)
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/**
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* amd_iommu_device_info() - Get information about IOMMUv2 support of a
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* PCI device
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* @pdev: PCI device to query information from
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* @info: A pointer to an amd_iommu_device_info structure which will contain
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* the information about the PCI device
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*
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* Returns 0 on success, negative value on error
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*/
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#define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */
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#define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */
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#define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */
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#define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8 /* Device may request execution
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on memory pages */
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#define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10 /* Device may request
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super-user privileges */
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struct amd_iommu_device_info {
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int max_pasids;
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u32 flags;
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};
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extern int amd_iommu_device_info(struct pci_dev *pdev,
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struct amd_iommu_device_info *info);
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/**
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* amd_iommu_set_invalidate_ctx_cb() - Register a call-back for invalidating
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* a pasid context. This call-back is
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* invoked when the IOMMUv2 driver needs to
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* invalidate a PASID context, for example
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* because the task that is bound to that
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* context is about to exit.
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*
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* @pdev: The PCI device the call-back should be registered for
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* @cb: The call-back function
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*/
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typedef void (*amd_iommu_invalidate_ctx)(struct pci_dev *pdev, u32 pasid);
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extern int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
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amd_iommu_invalidate_ctx cb);
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#else /* CONFIG_AMD_IOMMU */
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static inline int amd_iommu_detect(void) { return -ENODEV; }
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#endif /* CONFIG_AMD_IOMMU */
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#if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP)
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/* IOMMU AVIC Function */
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extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32));
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extern int
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amd_iommu_update_ga(int cpu, bool is_run, void *data);
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extern int amd_iommu_activate_guest_mode(void *data);
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extern int amd_iommu_deactivate_guest_mode(void *data);
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#else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
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static inline int
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amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
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{
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return 0;
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}
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static inline int
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amd_iommu_update_ga(int cpu, bool is_run, void *data)
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{
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return 0;
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}
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static inline int amd_iommu_activate_guest_mode(void *data)
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{
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return 0;
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}
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static inline int amd_iommu_deactivate_guest_mode(void *data)
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{
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return 0;
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}
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#endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
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int amd_iommu_get_num_iommus(void);
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bool amd_iommu_pc_supported(void);
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u8 amd_iommu_pc_get_max_banks(unsigned int idx);
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u8 amd_iommu_pc_get_max_counters(unsigned int idx);
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int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
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u64 *value);
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int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
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u64 *value);
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struct amd_iommu *get_amd_iommu(unsigned int idx);
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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int amd_iommu_snp_enable(void);
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#endif
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#endif /* _ASM_X86_AMD_IOMMU_H */
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