linux-stable/arch/x86/events
Kan Liang d88d05a9e0 perf/x86/intel: Fix a crash caused by zero PEBS status
A repeatable crash can be triggered by the perf_fuzzer on some Haswell
system.
https://lore.kernel.org/lkml/7170d3b-c17f-1ded-52aa-cc6d9ae999f4@maine.edu/

For some old CPUs (HSW and earlier), the PEBS status in a PEBS record
may be mistakenly set to 0. To minimize the impact of the defect, the
commit was introduced to try to avoid dropping the PEBS record for some
cases. It adds a check in the intel_pmu_drain_pebs_nhm(), and updates
the local pebs_status accordingly. However, it doesn't correct the PEBS
status in the PEBS record, which may trigger the crash, especially for
the large PEBS.

It's possible that all the PEBS records in a large PEBS have the PEBS
status 0. If so, the first get_next_pebs_record_by_bit() in the
__intel_pmu_pebs_event() returns NULL. The at = NULL. Since it's a large
PEBS, the 'count' parameter must > 1. The second
get_next_pebs_record_by_bit() will crash.

Besides the local pebs_status, correct the PEBS status in the PEBS
record as well.

Fixes: 01330d7288 ("perf/x86: Allow zero PEBS status with only single active event")
Reported-by: Vince Weaver <vincent.weaver@maine.edu>
Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/1615555298-140216-1-git-send-email-kan.liang@linux.intel.com
2021-03-16 21:44:39 +01:00
..
amd x86/CPU/AMD: Remove amd_get_nb_id() 2020-11-19 11:43:17 +01:00
intel perf/x86/intel: Fix a crash caused by zero PEBS status 2021-03-16 21:44:39 +01:00
zhaoxin x86/perf: Fix a typo 2020-07-22 10:22:08 +02:00
core.c x86/perf: Use RET0 as default for guest_get_msrs to handle "no PMU" case 2021-03-10 16:45:09 +01:00
Kconfig treewide: replace '---help---' in Kconfig files with 'help' 2020-06-14 01:57:21 +09:00
Makefile perf/x86/rapl: Fix RAPL config variable bug 2020-06-02 11:52:56 +02:00
msr.c perf/x86/msr: Add Rocket Lake CPU support 2020-10-29 11:00:40 +01:00
perf_event.h perf/x86/intel: Support CPUID 10.ECX to disable fixed counters 2021-02-01 15:31:37 +01:00
probe.c perf/x86/rapl: Add msr mask support 2021-02-10 14:44:54 +01:00
probe.h perf/x86/rapl: Add msr mask support 2021-02-10 14:44:54 +01:00
rapl.c perf/x86/rapl: Fix psys-energy event on Intel SPR platform 2021-02-10 14:44:55 +01:00