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![Tejun Heo](/assets/img/avatar_default.png)
Currently reset methods are not specified directly in the ata_port_operations table. If a LLD wants to use custom reset methods, it should construct and use a error_handler which uses those reset methods. It's done this way for two reasons. First, the ops table already contained too many methods and adding four more of them would noticeably increase the amount of necessary boilerplate code all over low level drivers. Second, as ->error_handler uses those reset methods, it can get confusing. ie. By overriding ->error_handler, those reset ops can be made useless making layering a bit hazy. Now that ops table uses inheritance, the first problem doesn't exist anymore. The second isn't completely solved but is relieved by providing default values - most drivers can just override what it has implemented and don't have to concern itself about higher level callbacks. In fact, there currently is no driver which actually modifies error handling behavior. Drivers which override ->error_handler just wraps the standard error handler only to prepare the controller for EH. I don't think making ops layering strict has any noticeable benefit. This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and their PMP counterparts propoer ops. Default ops are provided in the base ops tables and drivers are converted to override individual reset methods instead of creating custom error_handler. * ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs aren't accessible. sata_promise doesn't need to use separate error_handlers for PATA and SATA anymore. * softreset is broken for sata_inic162x and sata_sx4. As libata now always prefers hardreset, this doesn't really matter but the ops are forced to NULL using ATA_OP_NULL for documentation purpose. * pata_hpt374 needs to use different prereset for the first and second PCI functions. This used to be done by branching from hpt374_error_handler(). The proper way to do this is to use separate ops and port_info tables for each function. Converted. Signed-off-by: Tejun Heo <htejun@gmail.com>
251 lines
7.1 KiB
C
251 lines
7.1 KiB
C
/*
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* pata_mpiix.c - Intel MPIIX PATA for new ATA layer
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* (C) 2005-2006 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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*
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* The MPIIX is different enough to the PIIX4 and friends that we give it
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* a separate driver. The old ide/pci code handles this by just not tuning
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* MPIIX at all.
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*
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* The MPIIX also differs in another important way from the majority of PIIX
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* devices. The chip is a bridge (pardon the pun) between the old world of
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* ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
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* IDE controller is not decoded in PCI space and the chip does not claim to
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* be IDE class PCI. This requires slightly non-standard probe logic compared
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* with PCI IDE and also that we do not disable the device when our driver is
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* unloaded (as it has many other functions).
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*
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* The driver conciously keeps this logic internally to avoid pushing quirky
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* PATA history into the clean libata layer.
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*
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* Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
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* hard disk present this driver will not detect it. This is not a bug. In this
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* configuration the secondary port of the MPIIX is disabled and the addresses
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* are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
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* to operate.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_mpiix"
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#define DRV_VERSION "0.7.6"
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enum {
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IDETIM = 0x6C, /* IDE control register */
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IORDY = (1 << 1),
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PPE = (1 << 2),
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FTIM = (1 << 0),
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ENABLED = (1 << 15),
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SECONDARY = (1 << 14)
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};
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static int mpiix_pre_reset(struct ata_link *link, unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };
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if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
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return -ENOENT;
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return ata_std_prereset(link, deadline);
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}
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/**
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* mpiix_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the PIO mode setup. The MPIIX allows us to program the
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* IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
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* prefetching or IORDY are used.
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*
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* This would get very ugly because we can only program timing for one
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* device at a time, the other gets PIO0. Fortunately libata calls
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* our qc_issue_prot command before a command is issued so we can
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* flip the timings back and forth to reduce the pain.
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*/
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static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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int control = 0;
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int pio = adev->pio_mode - XFER_PIO_0;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u16 idetim;
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static const /* ISP RTC */
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u8 timings[][2] = { { 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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pci_read_config_word(pdev, IDETIM, &idetim);
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/* Mask the IORDY/TIME/PPE for this device */
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if (adev->class == ATA_DEV_ATA)
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control |= PPE; /* Enable prefetch/posting for disk */
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if (ata_pio_need_iordy(adev))
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control |= IORDY;
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if (pio > 1)
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control |= FTIM; /* This drive is on the fast timing bank */
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/* Mask out timing and clear both TIME bank selects */
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idetim &= 0xCCEE;
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idetim &= ~(0x07 << (4 * adev->devno));
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idetim |= control << (4 * adev->devno);
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idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
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pci_write_config_word(pdev, IDETIM, idetim);
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/* We use ap->private_data as a pointer to the device currently
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loaded for timing */
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ap->private_data = adev;
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}
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/**
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* mpiix_qc_issue_prot - command issue
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* @qc: command pending
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*
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* Called when the libata layer is about to issue a command. We wrap
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* this interface so that we can load the correct ATA timings if
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* necessary. Our logic also clears TIME0/TIME1 for the other device so
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* that, even if we get this wrong, cycles to the other device will
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* be made PIO0.
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*/
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static unsigned int mpiix_qc_issue_prot(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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/* If modes have been configured and the channel data is not loaded
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then load it. We have to check if pio_mode is set as the core code
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does not set adev->pio_mode to XFER_PIO_0 while probing as would be
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logical */
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if (adev->pio_mode && adev != ap->private_data)
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mpiix_set_piomode(ap, adev);
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return ata_qc_issue_prot(qc);
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}
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static struct scsi_host_template mpiix_sht = {
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ATA_PIO_SHT(DRV_NAME),
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};
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static struct ata_port_operations mpiix_port_ops = {
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.inherits = &ata_sff_port_ops,
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.qc_issue = mpiix_qc_issue_prot,
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.cable_detect = ata_cable_40wire,
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.set_piomode = mpiix_set_piomode,
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.prereset = mpiix_pre_reset,
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};
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static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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/* Single threaded by the PCI probe logic */
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static int printed_version;
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struct ata_host *host;
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struct ata_port *ap;
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void __iomem *cmd_addr, *ctl_addr;
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u16 idetim;
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int cmd, ctl, irq;
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
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host = ata_host_alloc(&dev->dev, 1);
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if (!host)
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return -ENOMEM;
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ap = host->ports[0];
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/* MPIIX has many functions which can be turned on or off according
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to other devices present. Make sure IDE is enabled before we try
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and use it */
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pci_read_config_word(dev, IDETIM, &idetim);
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if (!(idetim & ENABLED))
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return -ENODEV;
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/* See if it's primary or secondary channel... */
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if (!(idetim & SECONDARY)) {
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cmd = 0x1F0;
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ctl = 0x3F6;
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irq = 14;
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} else {
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cmd = 0x170;
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ctl = 0x376;
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irq = 15;
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}
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cmd_addr = devm_ioport_map(&dev->dev, cmd, 8);
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ctl_addr = devm_ioport_map(&dev->dev, ctl, 1);
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if (!cmd_addr || !ctl_addr)
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return -ENOMEM;
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ata_port_desc(ap, "cmd 0x%x ctl 0x%x", cmd, ctl);
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/* We do our own plumbing to avoid leaking special cases for whacko
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ancient hardware into the core code. There are two issues to
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worry about. #1 The chip is a bridge so if in legacy mode and
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without BARs set fools the setup. #2 If you pci_disable_device
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the MPIIX your box goes castors up */
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ap->ops = &mpiix_port_ops;
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ap->pio_mask = 0x1F;
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ap->flags |= ATA_FLAG_SLAVE_POSS;
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ap->ioaddr.cmd_addr = cmd_addr;
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ap->ioaddr.ctl_addr = ctl_addr;
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ap->ioaddr.altstatus_addr = ctl_addr;
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/* Let libata fill in the port details */
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ata_std_ports(&ap->ioaddr);
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/* activate host */
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return ata_host_activate(host, irq, ata_interrupt, IRQF_SHARED,
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&mpiix_sht);
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}
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static const struct pci_device_id mpiix[] = {
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
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{ },
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};
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static struct pci_driver mpiix_pci_driver = {
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.name = DRV_NAME,
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.id_table = mpiix,
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.probe = mpiix_init_one,
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.remove = ata_pci_remove_one,
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#ifdef CONFIG_PM
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.suspend = ata_pci_device_suspend,
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.resume = ata_pci_device_resume,
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#endif
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};
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static int __init mpiix_init(void)
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{
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return pci_register_driver(&mpiix_pci_driver);
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}
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static void __exit mpiix_exit(void)
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{
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pci_unregister_driver(&mpiix_pci_driver);
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}
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, mpiix);
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MODULE_VERSION(DRV_VERSION);
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module_init(mpiix_init);
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module_exit(mpiix_exit);
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