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![Tejun Heo](/assets/img/avatar_default.png)
libata lets low level drivers build ata_port_operations table and register it with libata core layer. This allows low level drivers high level of flexibility but also burdens them with lots of boilerplate entries. This becomes worse for drivers which support related similar controllers which differ slightly. They share most of the operations except for a few. However, the driver still needs to list all operations for each variant. This results in large number of duplicate entries, which is not only inefficient but also error-prone as it becomes very difficult to tell what the actual differences are. This duplicate boilerplates all over the low level drivers also make updating the core layer exteremely difficult and error-prone. When compounded with multi-branched development model, it ends up accumulating inconsistencies over time. Some of those inconsistencies cause immediate problems and fixed. Others just remain there dormant making maintenance increasingly difficult. To rectify the problem, this patch implements ata_port_operations inheritance. To allow LLDs to easily re-use their own ops tables overriding only specific methods, this patch implements poor man's class inheritance. An ops table has ->inherits field which can be set to any ops table as long as it doesn't create a loop. When the host is started, the inheritance chain is followed and any operation which isn't specified is taken from the nearest ancestor which has it specified. This operation is called finalization and done only once per an ops table and the LLD doesn't have to do anything special about it other than making the ops table non-const such that libata can update it. libata provides four base ops tables lower drivers can inherit from - base, sata, pmp, sff and bmdma. To avoid overriding these ops accidentaly, these ops are declared const and LLDs should always inherit these instead of using them directly. After finalization, all the ops table are identical before and after the patch except for setting .irq_handler to ata_interrupt in drivers which didn't use to. The .irq_handler doesn't have any actual effect and the field will soon be removed by later patch. * sata_sx4 is still using old style EH and currently doesn't take advantage of ops inheritance. Signed-off-by: Tejun Heo <htejun@gmail.com>
179 lines
4.6 KiB
C
179 lines
4.6 KiB
C
/*
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* pata_ninja32.c - Ninja32 PATA for new ATA layer
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* (C) 2007 Red Hat Inc
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* Alan Cox <alan@redhat.com>
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*
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* Note: The controller like many controllers has shared timings for
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* PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
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* in the dma_stop function. Thus we actually don't need a set_dmamode
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* method as the PIO method is always called and will set the right PIO
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* timing parameters.
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*
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* The Ninja32 Cardbus is not a generic SFF controller. Instead it is
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* laid out as follows off BAR 0. This is based upon Mark Lord's delkin
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* driver and the extensive analysis done by the BSD developers, notably
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* ITOH Yasufumi.
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*
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* Base + 0x00 IRQ Status
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* Base + 0x01 IRQ control
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* Base + 0x02 Chipset control
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* Base + 0x03 Unknown
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* Base + 0x04 VDMA and reset control + wait bits
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* Base + 0x08 BMIMBA
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* Base + 0x0C DMA Length
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* Base + 0x10 Taskfile
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* Base + 0x18 BMDMA Status ?
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* Base + 0x1C
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* Base + 0x1D Bus master control
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* bit 0 = enable
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* bit 1 = 0 write/1 read
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* bit 2 = 1 sgtable
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* bit 3 = go
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* bit 4-6 wait bits
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* bit 7 = done
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* Base + 0x1E AltStatus
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* Base + 0x1F timing register
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_ninja32"
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#define DRV_VERSION "0.0.1"
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/**
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* ninja32_set_piomode - set initial PIO mode data
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* @ap: ATA interface
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* @adev: ATA device
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*
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* Called to do the PIO mode setup. Our timing registers are shared
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* but we want to set the PIO timing by default.
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*/
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static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev)
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{
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static u16 pio_timing[5] = {
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0xd6, 0x85, 0x44, 0x33, 0x13
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};
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iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0],
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ap->ioaddr.bmdma_addr + 0x1f);
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ap->private_data = adev;
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}
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static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
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{
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struct ata_device *adev = &ap->link.device[device];
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if (ap->private_data != adev) {
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iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f);
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ata_std_dev_select(ap, device);
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ninja32_set_piomode(ap, adev);
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}
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}
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static struct scsi_host_template ninja32_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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static struct ata_port_operations ninja32_port_ops = {
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.inherits = &ata_bmdma_port_ops,
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.dev_select = ninja32_dev_select,
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.cable_detect = ata_cable_40wire,
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.set_piomode = ninja32_set_piomode,
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};
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static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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struct ata_host *host;
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struct ata_port *ap;
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void __iomem *base;
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int rc;
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host = ata_host_alloc(&dev->dev, 1);
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if (!host)
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return -ENOMEM;
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ap = host->ports[0];
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/* Set up the PCI device */
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rc = pcim_enable_device(dev);
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if (rc)
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return rc;
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rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME);
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if (rc == -EBUSY)
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pcim_pin_device(dev);
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if (rc)
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return rc;
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host->iomap = pcim_iomap_table(dev);
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rc = pci_set_dma_mask(dev, ATA_DMA_MASK);
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if (rc)
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return rc;
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rc = pci_set_consistent_dma_mask(dev, ATA_DMA_MASK);
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if (rc)
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return rc;
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pci_set_master(dev);
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/* Set up the register mappings */
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base = host->iomap[0];
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if (!base)
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return -ENOMEM;
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ap->ops = &ninja32_port_ops;
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ap->pio_mask = 0x1F;
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ap->flags |= ATA_FLAG_SLAVE_POSS;
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ap->ioaddr.cmd_addr = base + 0x10;
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ap->ioaddr.ctl_addr = base + 0x1E;
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ap->ioaddr.altstatus_addr = base + 0x1E;
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ap->ioaddr.bmdma_addr = base;
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ata_std_ports(&ap->ioaddr);
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iowrite8(0x05, base + 0x01); /* Enable interrupt lines */
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iowrite8(0xBE, base + 0x02); /* Burst, ?? setup */
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iowrite8(0x01, base + 0x03); /* Unknown */
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iowrite8(0x20, base + 0x04); /* WAIT0 */
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iowrite8(0x8f, base + 0x05); /* Unknown */
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iowrite8(0xa4, base + 0x1c); /* Unknown */
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iowrite8(0x83, base + 0x1d); /* BMDMA control: WAIT0 */
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/* FIXME: Should we disable them at remove ? */
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return ata_host_activate(host, dev->irq, ata_interrupt,
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IRQF_SHARED, &ninja32_sht);
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}
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static const struct pci_device_id ninja32[] = {
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{ 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
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{ 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
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{ },
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};
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static struct pci_driver ninja32_pci_driver = {
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.name = DRV_NAME,
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.id_table = ninja32,
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.probe = ninja32_init_one,
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.remove = ata_pci_remove_one
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};
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static int __init ninja32_init(void)
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{
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return pci_register_driver(&ninja32_pci_driver);
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}
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static void __exit ninja32_exit(void)
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{
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pci_unregister_driver(&ninja32_pci_driver);
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}
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, ninja32);
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MODULE_VERSION(DRV_VERSION);
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module_init(ninja32_init);
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module_exit(ninja32_exit);
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