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5ce4b59653
The 440EPx/GRx chips don't support PCI MRM commands. Drivers determine this by looking for a zero value in the PCI cache line size register. However, some drivers write to this register upon initialization. This can cause MRMs to be used on these chips, which may cause deadlocks on PLB4. The workaround implemented here introduces a new indirect_type flag, called PPC_INDIRECT_TYPE_BROKEN_MRM. This is set in the pci_controller structure in the pci fixup function for 4xx PCI bridges by determining if the bridge is compatible with 440EPx/GRx. The flag is checked in the indirect_write_config function, and forces any writes to the PCI_CACHE_LINE_SIZE register to be zero, which will disable MRMs for these chips. A similar workaround has been tested by AMCC on various PCI cards, such as the Silicon Image ATA card and Intel E1000 GIGE card. Hangs were seen with the Silicon Image card, and MRMs were seen on the bus with a PCI analyzer. With the workaround in place, the card functioned properly and only Memory Reads were seen on the bus with the analyzer. Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
172 lines
4.4 KiB
C
172 lines
4.4 KiB
C
/*
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* Support for indirect PCI bridges.
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*
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* Copyright (C) 1998 Gabriel Paubert.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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static int
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indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 *val)
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{
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struct pci_controller *hose = bus->sysdata;
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volatile void __iomem *cfg_data;
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u8 cfg_type = 0;
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u32 bus_no, reg;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
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if (bus->number != hose->first_busno)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (devfn != 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
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if (bus->number != hose->first_busno)
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cfg_type = 1;
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bus_no = (bus->number == hose->first_busno) ?
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hose->self_busno : bus->number;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
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reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
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else
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reg = offset & 0xfc;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
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out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
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(devfn << 8) | reg | cfg_type));
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else
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out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
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(devfn << 8) | reg | cfg_type));
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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cfg_data = hose->cfg_data + (offset & 3);
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switch (len) {
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case 1:
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*val = in_8(cfg_data);
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break;
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case 2:
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*val = in_le16(cfg_data);
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break;
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default:
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*val = in_le32(cfg_data);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 val)
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{
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struct pci_controller *hose = bus->sysdata;
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volatile void __iomem *cfg_data;
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u8 cfg_type = 0;
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u32 bus_no, reg;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
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if (bus->number != hose->first_busno)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (devfn != 0)
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
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if (bus->number != hose->first_busno)
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cfg_type = 1;
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bus_no = (bus->number == hose->first_busno) ?
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hose->self_busno : bus->number;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
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reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
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else
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reg = offset & 0xfc;
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if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
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out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
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(devfn << 8) | reg | cfg_type));
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else
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out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
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(devfn << 8) | reg | cfg_type));
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/* surpress setting of PCI_PRIMARY_BUS */
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if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
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if ((offset == PCI_PRIMARY_BUS) &&
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(bus->number == hose->first_busno))
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val &= 0xffffff00;
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/* Workaround for PCI_28 Errata in 440EPx/GRx */
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if ((hose->indirect_type & PPC_INDIRECT_TYPE_BROKEN_MRM) &&
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offset == PCI_CACHE_LINE_SIZE) {
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val = 0;
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}
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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cfg_data = hose->cfg_data + (offset & 3);
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switch (len) {
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case 1:
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out_8(cfg_data, val);
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break;
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case 2:
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out_le16(cfg_data, val);
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break;
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default:
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out_le32(cfg_data, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops indirect_pci_ops =
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{
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.read = indirect_read_config,
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.write = indirect_write_config,
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};
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void __init
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setup_indirect_pci(struct pci_controller* hose,
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resource_size_t cfg_addr,
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resource_size_t cfg_data, u32 flags)
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{
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resource_size_t base = cfg_addr & PAGE_MASK;
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void __iomem *mbase;
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mbase = ioremap(base, PAGE_SIZE);
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hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
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if ((cfg_data & PAGE_MASK) != base)
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mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
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hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
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hose->ops = &indirect_pci_ops;
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hose->indirect_type = flags;
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}
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