mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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d1f936d736
* Fix memory leaks in the core * Remove unused NAND locking support * Rename nand.h into rawnand.h (preparing support for spi NANDs) * Use NAND_MAX_ID_LEN where appropriate * Fix support for 20nm Hynix chips * Fix support for Samsung and Hynix SLC NANDs and the following driver changes: * Various cleanup, improvements and fixes in the qcom driver * Fixes for bugs detected by various static code analysis tools * Fix mxc ooblayout definition * Add a new part_parsers to tmio and sharpsl platform data in order to define a custom list of partition parsers * Request the reset line in exclusive mode in the sunxi driver * Fix a build error in the orion-nand driver when compiled for ARMv4 * Allow 64-bit mvebu platforms to select the PXA3XX driver -----BEGIN PGP SIGNATURE----- iQJABAABCAAqBQJZpwMZIxxib3Jpcy5icmV6aWxsb25AZnJlZS1lbGVjdHJvbnMu Y29tAAoJEGXtNgF+CLcAJEoP/jRnEjPznWT3+ngw6k/rnykkn/wexKV3iyX/6b71 MQT/ZFuT3HsHnUjyprPvyRWJeKun6XyIH5fk7FlXIei9TaWCt6/UGTKousaPKeR2 maggGeEjxGVpHJM/jpIYCyjt83zpezBqTupv52XhXxPaU7ROSpuHCd92YcPzIaT5 tcn8JrI7TGuGlBrBbA2y8ZrPtuug3IKqUfpIiQmoqr0jzQR+AbZKHg0kk5a8piOn OguK67uhxeOvq831bGPehCPDbuE0loNi4CssayJ1HrisfS95kH/cqrveapgKsUG/ fxaHh1i65I0lxa8sgUgeUiU04Zsy1YcgNbCj41AY4AHnjJ0+Qp1cV6KAB/x5/wH9 ES/fW06how+1BLEeLvOr+rIQ41WeP0qV2H3r/PtkeswKKAV3gSERBXVHmg1E7Yum HkmPqzhu+nSk3mP7p3yxpd7EwWQh2xpvVYrfQ5vQbtdfm8Uw9n6S8x+O89ch9wWi +KbMWFsmF78nuRWW3WTsaiOFKcTRLBT5RoU2z4i9hCvQT2Pnx3SBhHrIj6xqBI1S 8MpeDdlXHmRQfZxj+jDqU77JYqVEmy/5it9OjhjMpOqxfCf4K6Nlb75TEdR5Nh/9 BA1qqTBEslg3UqS8ofGFHGFZWrW3JHf02SYo2zU9IvBninh3HrqHiFhBc3p1xNDE 7GwD =bC1+ -----END PGP SIGNATURE----- Merge tag 'nand/for-4.14' of git://git.infradead.org/l2-mtd into mtd/next From Boris: " This pull request contains the following core changes: * Fix memory leaks in the core * Remove unused NAND locking support * Rename nand.h into rawnand.h (preparing support for spi NANDs) * Use NAND_MAX_ID_LEN where appropriate * Fix support for 20nm Hynix chips * Fix support for Samsung and Hynix SLC NANDs and the following driver changes: * Various cleanup, improvements and fixes in the qcom driver * Fixes for bugs detected by various static code analysis tools * Fix mxc ooblayout definition * Add a new part_parsers to tmio and sharpsl platform data in order to define a custom list of partition parsers * Request the reset line in exclusive mode in the sunxi driver * Fix a build error in the orion-nand driver when compiled for ARMv4 * Allow 64-bit mvebu platforms to select the PXA3XX driver "
335 lines
7.4 KiB
C
335 lines
7.4 KiB
C
/*
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* Copyright (C) 2014 Free Electrons
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*
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/mtd/rawnand.h>
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static const struct nand_data_interface onfi_sdr_timings[] = {
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/* Mode 0 */
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{
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.type = NAND_SDR_IFACE,
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.timings.sdr = {
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 20000,
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.tALS_min = 50000,
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.tAR_min = 25000,
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.tCEA_max = 100000,
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.tCEH_min = 20000,
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.tCH_min = 20000,
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.tCHZ_max = 100000,
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.tCLH_min = 20000,
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.tCLR_min = 20000,
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.tCLS_min = 50000,
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.tCOH_min = 0,
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.tCS_min = 70000,
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.tDH_min = 20000,
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.tDS_min = 40000,
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.tFEAT_max = 1000000,
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.tIR_min = 10000,
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.tITC_max = 1000000,
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.tRC_min = 100000,
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.tREA_max = 40000,
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.tREH_min = 30000,
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.tRHOH_min = 0,
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.tRHW_min = 200000,
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.tRHZ_max = 200000,
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.tRLOH_min = 0,
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.tRP_min = 50000,
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.tRR_min = 40000,
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.tRST_max = 250000000000ULL,
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.tWB_max = 200000,
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.tWC_min = 100000,
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.tWH_min = 30000,
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.tWHR_min = 120000,
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.tWP_min = 50000,
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.tWW_min = 100000,
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},
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},
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/* Mode 1 */
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{
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.type = NAND_SDR_IFACE,
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.timings.sdr = {
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 10000,
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.tALS_min = 25000,
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.tAR_min = 10000,
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.tCEA_max = 45000,
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.tCEH_min = 20000,
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.tCH_min = 10000,
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.tCHZ_max = 50000,
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.tCLH_min = 10000,
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.tCLR_min = 10000,
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.tCLS_min = 25000,
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.tCOH_min = 15000,
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.tCS_min = 35000,
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.tDH_min = 10000,
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.tDS_min = 20000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 50000,
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.tREA_max = 30000,
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.tREH_min = 15000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 0,
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.tRP_min = 25000,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tWC_min = 45000,
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.tWH_min = 15000,
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.tWHR_min = 80000,
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.tWP_min = 25000,
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.tWW_min = 100000,
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},
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},
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/* Mode 2 */
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{
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.type = NAND_SDR_IFACE,
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.timings.sdr = {
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 10000,
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.tALS_min = 15000,
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.tAR_min = 10000,
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.tCEA_max = 30000,
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.tCEH_min = 20000,
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.tCH_min = 10000,
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.tCHZ_max = 50000,
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.tCLH_min = 10000,
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.tCLR_min = 10000,
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.tCLS_min = 15000,
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.tCOH_min = 15000,
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.tCS_min = 25000,
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.tDH_min = 5000,
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.tDS_min = 15000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 35000,
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.tREA_max = 25000,
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.tREH_min = 15000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 0,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tRP_min = 17000,
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.tWC_min = 35000,
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.tWH_min = 15000,
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.tWHR_min = 80000,
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.tWP_min = 17000,
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.tWW_min = 100000,
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},
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},
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/* Mode 3 */
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{
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.type = NAND_SDR_IFACE,
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.timings.sdr = {
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 5000,
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.tALS_min = 10000,
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.tAR_min = 10000,
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.tCEA_max = 25000,
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.tCEH_min = 20000,
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.tCH_min = 5000,
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.tCHZ_max = 50000,
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.tCLH_min = 5000,
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.tCLR_min = 10000,
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.tCLS_min = 10000,
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.tCOH_min = 15000,
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.tCS_min = 25000,
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.tDH_min = 5000,
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.tDS_min = 10000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 30000,
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.tREA_max = 20000,
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.tREH_min = 10000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 0,
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.tRP_min = 15000,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tWC_min = 30000,
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.tWH_min = 10000,
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.tWHR_min = 80000,
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.tWP_min = 15000,
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.tWW_min = 100000,
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},
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},
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/* Mode 4 */
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{
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.type = NAND_SDR_IFACE,
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.timings.sdr = {
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 5000,
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.tALS_min = 10000,
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.tAR_min = 10000,
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.tCEA_max = 25000,
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.tCEH_min = 20000,
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.tCH_min = 5000,
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.tCHZ_max = 30000,
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.tCLH_min = 5000,
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.tCLR_min = 10000,
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.tCLS_min = 10000,
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.tCOH_min = 15000,
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.tCS_min = 20000,
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.tDH_min = 5000,
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.tDS_min = 10000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 25000,
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.tREA_max = 20000,
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.tREH_min = 10000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 5000,
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.tRP_min = 12000,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tWC_min = 25000,
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.tWH_min = 10000,
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.tWHR_min = 80000,
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.tWP_min = 12000,
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.tWW_min = 100000,
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},
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},
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/* Mode 5 */
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{
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.type = NAND_SDR_IFACE,
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.timings.sdr = {
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.tCCS_min = 500000,
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.tR_max = 200000000,
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.tADL_min = 400000,
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.tALH_min = 5000,
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.tALS_min = 10000,
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.tAR_min = 10000,
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.tCEA_max = 25000,
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.tCEH_min = 20000,
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.tCH_min = 5000,
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.tCHZ_max = 30000,
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.tCLH_min = 5000,
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.tCLR_min = 10000,
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.tCLS_min = 10000,
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.tCOH_min = 15000,
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.tCS_min = 15000,
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.tDH_min = 5000,
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.tDS_min = 7000,
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.tFEAT_max = 1000000,
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.tIR_min = 0,
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.tITC_max = 1000000,
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.tRC_min = 20000,
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.tREA_max = 16000,
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.tREH_min = 7000,
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.tRHOH_min = 15000,
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.tRHW_min = 100000,
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.tRHZ_max = 100000,
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.tRLOH_min = 5000,
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.tRP_min = 10000,
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.tRR_min = 20000,
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.tRST_max = 500000000,
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.tWB_max = 100000,
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.tWC_min = 20000,
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.tWH_min = 7000,
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.tWHR_min = 80000,
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.tWP_min = 10000,
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.tWW_min = 100000,
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},
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},
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};
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/**
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* onfi_async_timing_mode_to_sdr_timings - [NAND Interface] Retrieve NAND
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* timings according to the given ONFI timing mode
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* @mode: ONFI timing mode
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*/
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const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode)
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{
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if (mode < 0 || mode >= ARRAY_SIZE(onfi_sdr_timings))
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return ERR_PTR(-EINVAL);
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return &onfi_sdr_timings[mode].timings.sdr;
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}
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EXPORT_SYMBOL(onfi_async_timing_mode_to_sdr_timings);
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/**
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* onfi_init_data_interface - [NAND Interface] Initialize a data interface from
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* given ONFI mode
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* @iface: The data interface to be initialized
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* @mode: The ONFI timing mode
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*/
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int onfi_init_data_interface(struct nand_chip *chip,
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struct nand_data_interface *iface,
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enum nand_data_interface_type type,
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int timing_mode)
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{
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if (type != NAND_SDR_IFACE)
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return -EINVAL;
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if (timing_mode < 0 || timing_mode >= ARRAY_SIZE(onfi_sdr_timings))
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return -EINVAL;
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*iface = onfi_sdr_timings[timing_mode];
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/*
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* Initialize timings that cannot be deduced from timing mode:
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* tR, tPROG, tCCS, ...
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* These information are part of the ONFI parameter page.
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*/
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if (chip->onfi_version) {
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struct nand_onfi_params *params = &chip->onfi_params;
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struct nand_sdr_timings *timings = &iface->timings.sdr;
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/* microseconds -> picoseconds */
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timings->tPROG_max = 1000000ULL * le16_to_cpu(params->t_prog);
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timings->tBERS_max = 1000000ULL * le16_to_cpu(params->t_bers);
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timings->tR_max = 1000000ULL * le16_to_cpu(params->t_r);
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/* nanoseconds -> picoseconds */
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timings->tCCS_min = 1000UL * le16_to_cpu(params->t_ccs);
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}
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return 0;
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}
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EXPORT_SYMBOL(onfi_init_data_interface);
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/**
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* nand_get_default_data_interface - [NAND Interface] Retrieve NAND
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* data interface for mode 0. This is used as default timing after
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* reset.
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*/
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const struct nand_data_interface *nand_get_default_data_interface(void)
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{
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return &onfi_sdr_timings[0];
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}
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EXPORT_SYMBOL(nand_get_default_data_interface);
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