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![Daniel Vetter](/assets/img/avatar_default.png)
With the rework to merge the bit-banging fallback into the gmbus
i2c adapter we've gotten rid of the deadlock possibility that
originally lead to the disabling of this code.
This reverts the revert
commit 826c7e4147
Author: Jean Delvare <khali@linux-fr.org>
Date: Sat Jun 4 19:34:56 2011 +0000
Revert "drm/i915: Enable GMBUS for post-gen2 chipsets"
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=35572
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
441 lines
11 KiB
C
441 lines
11 KiB
C
/*
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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* Copyright © 2006-2008,2010 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Chris Wilson <chris@chris-wilson.co.uk>
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*/
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/export.h>
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#include "drmP.h"
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#include "drm.h"
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#include "intel_drv.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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/* Intel GPIO access functions */
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#define I2C_RISEFALL_TIME 10
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static inline struct intel_gmbus *
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to_intel_gmbus(struct i2c_adapter *i2c)
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{
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return container_of(i2c, struct intel_gmbus, adapter);
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}
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void
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intel_i2c_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (HAS_PCH_SPLIT(dev))
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I915_WRITE(PCH_GMBUS0, 0);
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else
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I915_WRITE(GMBUS0, 0);
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}
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static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
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{
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u32 val;
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/* When using bit bashing for I2C, this bit needs to be set to 1 */
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if (!IS_PINEVIEW(dev_priv->dev))
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return;
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val = I915_READ(DSPCLK_GATE_D);
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if (enable)
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val |= DPCUNIT_CLOCK_GATE_DISABLE;
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else
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val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(DSPCLK_GATE_D, val);
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}
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static u32 get_reserved(struct intel_gmbus *bus)
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{
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struct drm_i915_private *dev_priv = bus->dev_priv;
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struct drm_device *dev = dev_priv->dev;
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u32 reserved = 0;
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/* On most chips, these bits must be preserved in software. */
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if (!IS_I830(dev) && !IS_845G(dev))
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reserved = I915_READ_NOTRACE(bus->gpio_reg) &
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(GPIO_DATA_PULLUP_DISABLE |
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GPIO_CLOCK_PULLUP_DISABLE);
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return reserved;
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}
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static int get_clock(void *data)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
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return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
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}
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static int get_data(void *data)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
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return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
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}
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static void set_clock(void *data, int state_high)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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u32 clock_bits;
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if (state_high)
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clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
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else
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clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
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GPIO_CLOCK_VAL_MASK;
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
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POSTING_READ(bus->gpio_reg);
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}
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static void set_data(void *data, int state_high)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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u32 data_bits;
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if (state_high)
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data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
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else
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data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
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GPIO_DATA_VAL_MASK;
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
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POSTING_READ(bus->gpio_reg);
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}
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static bool
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intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
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{
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struct drm_i915_private *dev_priv = bus->dev_priv;
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static const int map_pin_to_reg[] = {
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0,
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GPIOB,
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GPIOA,
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GPIOC,
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GPIOD,
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GPIOE,
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0,
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GPIOF,
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};
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struct i2c_algo_bit_data *algo;
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if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
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return false;
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algo = &bus->bit_algo;
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bus->gpio_reg = map_pin_to_reg[pin];
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if (HAS_PCH_SPLIT(dev_priv->dev))
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bus->gpio_reg += PCH_GPIOA - GPIOA;
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bus->adapter.algo_data = algo;
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algo->setsda = set_data;
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algo->setscl = set_clock;
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algo->getsda = get_data;
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algo->getscl = get_clock;
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algo->udelay = I2C_RISEFALL_TIME;
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algo->timeout = usecs_to_jiffies(2200);
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algo->data = bus;
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return true;
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}
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static int
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intel_i2c_quirk_xfer(struct intel_gmbus *bus,
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struct i2c_msg *msgs,
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int num)
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{
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struct drm_i915_private *dev_priv = bus->dev_priv;
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int ret;
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intel_i2c_reset(dev_priv->dev);
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intel_i2c_quirk_set(dev_priv, true);
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set_data(bus, 1);
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set_clock(bus, 1);
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udelay(I2C_RISEFALL_TIME);
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ret = i2c_bit_algo.master_xfer(&bus->adapter, msgs, num);
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set_data(bus, 1);
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set_clock(bus, 1);
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intel_i2c_quirk_set(dev_priv, false);
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return ret;
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}
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static int
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gmbus_xfer(struct i2c_adapter *adapter,
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struct i2c_msg *msgs,
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int num)
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{
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struct intel_gmbus *bus = container_of(adapter,
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struct intel_gmbus,
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adapter);
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struct drm_i915_private *dev_priv = bus->dev_priv;
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int i, reg_offset, ret;
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mutex_lock(&dev_priv->gmbus_mutex);
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if (bus->force_bit) {
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ret = intel_i2c_quirk_xfer(bus, msgs, num);
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goto out;
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}
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reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
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I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
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for (i = 0; i < num; i++) {
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u16 len = msgs[i].len;
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u8 *buf = msgs[i].buf;
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if (msgs[i].flags & I2C_M_RD) {
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I915_WRITE(GMBUS1 + reg_offset,
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GMBUS_CYCLE_WAIT |
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(i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
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(len << GMBUS_BYTE_COUNT_SHIFT) |
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(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_READ | GMBUS_SW_RDY);
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POSTING_READ(GMBUS2+reg_offset);
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do {
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u32 val, loop = 0;
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if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
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goto timeout;
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if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
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goto clear_err;
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val = I915_READ(GMBUS3 + reg_offset);
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do {
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*buf++ = val & 0xff;
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val >>= 8;
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} while (--len && ++loop < 4);
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} while (len);
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} else {
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u32 val, loop;
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val = loop = 0;
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do {
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val |= *buf++ << (8 * loop);
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} while (--len && ++loop < 4);
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I915_WRITE(GMBUS3 + reg_offset, val);
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I915_WRITE(GMBUS1 + reg_offset,
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GMBUS_CYCLE_WAIT |
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(i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
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(msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
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(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
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POSTING_READ(GMBUS2+reg_offset);
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while (len) {
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if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
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goto timeout;
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if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
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goto clear_err;
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val = loop = 0;
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do {
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val |= *buf++ << (8 * loop);
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} while (--len && ++loop < 4);
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I915_WRITE(GMBUS3 + reg_offset, val);
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POSTING_READ(GMBUS2+reg_offset);
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}
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}
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if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
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goto timeout;
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if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
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goto clear_err;
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}
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goto done;
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clear_err:
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/* Toggle the Software Clear Interrupt bit. This has the effect
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* of resetting the GMBUS controller and so clearing the
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* BUS_ERROR raised by the slave's NAK.
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*/
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I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
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I915_WRITE(GMBUS1 + reg_offset, 0);
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done:
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/* Mark the GMBUS interface as disabled after waiting for idle.
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* We will re-enable it at the start of the next xfer,
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* till then let it sleep.
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*/
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if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, 10))
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DRM_INFO("GMBUS timed out waiting for idle\n");
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I915_WRITE(GMBUS0 + reg_offset, 0);
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ret = i;
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goto out;
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timeout:
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DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
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bus->reg0 & 0xff, bus->adapter.name);
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I915_WRITE(GMBUS0 + reg_offset, 0);
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/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
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if (!bus->has_gpio) {
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ret = -EIO;
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} else {
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bus->force_bit = true;
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ret = intel_i2c_quirk_xfer(bus, msgs, num);
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}
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out:
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mutex_unlock(&dev_priv->gmbus_mutex);
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return ret;
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}
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static u32 gmbus_func(struct i2c_adapter *adapter)
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{
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return i2c_bit_algo.functionality(adapter) &
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(I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
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/* I2C_FUNC_10BIT_ADDR | */
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I2C_FUNC_SMBUS_READ_BLOCK_DATA |
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I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
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}
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static const struct i2c_algorithm gmbus_algorithm = {
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.master_xfer = gmbus_xfer,
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.functionality = gmbus_func
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};
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/**
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* intel_gmbus_setup - instantiate all Intel i2c GMBuses
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* @dev: DRM device
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*/
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int intel_setup_gmbus(struct drm_device *dev)
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{
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static const char *names[GMBUS_NUM_PORTS] = {
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"disabled",
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"ssc",
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"vga",
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"panel",
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"dpc",
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"dpb",
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"reserved",
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"dpd",
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};
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret, i;
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dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
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GFP_KERNEL);
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if (dev_priv->gmbus == NULL)
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return -ENOMEM;
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mutex_init(&dev_priv->gmbus_mutex);
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for (i = 0; i < GMBUS_NUM_PORTS; i++) {
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struct intel_gmbus *bus = &dev_priv->gmbus[i];
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bus->adapter.owner = THIS_MODULE;
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bus->adapter.class = I2C_CLASS_DDC;
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snprintf(bus->adapter.name,
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sizeof(bus->adapter.name),
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"i915 gmbus %s",
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names[i]);
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bus->adapter.dev.parent = &dev->pdev->dev;
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bus->dev_priv = dev_priv;
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bus->adapter.algo = &gmbus_algorithm;
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ret = i2c_add_adapter(&bus->adapter);
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if (ret)
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goto err;
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/* By default use a conservative clock rate */
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bus->reg0 = i | GMBUS_RATE_100KHZ;
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bus->has_gpio = intel_gpio_setup(bus, i);
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/* XXX force bit banging until GMBUS is fully debugged */
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if (bus->has_gpio && IS_GEN2(dev))
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bus->force_bit = true;
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}
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intel_i2c_reset(dev_priv->dev);
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return 0;
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err:
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while (--i) {
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struct intel_gmbus *bus = &dev_priv->gmbus[i];
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i2c_del_adapter(&bus->adapter);
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}
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kfree(dev_priv->gmbus);
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dev_priv->gmbus = NULL;
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return ret;
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}
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void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
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{
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struct intel_gmbus *bus = to_intel_gmbus(adapter);
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bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
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}
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void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
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{
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struct intel_gmbus *bus = to_intel_gmbus(adapter);
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if (bus->has_gpio)
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bus->force_bit = force_bit;
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}
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void intel_teardown_gmbus(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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if (dev_priv->gmbus == NULL)
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return;
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for (i = 0; i < GMBUS_NUM_PORTS; i++) {
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struct intel_gmbus *bus = &dev_priv->gmbus[i];
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i2c_del_adapter(&bus->adapter);
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}
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kfree(dev_priv->gmbus);
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dev_priv->gmbus = NULL;
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}
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