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![Daniel Vetter](/assets/img/avatar_default.png)
We have a pretty decent confusion about vertical timings of interlaced modes. Peter Ross has written a patch that makes interlace modes work on a lot more platforms/output combinations by doubling the vertical timings. The issue with that patch is that core drm _does_ support specifying whether we want these vertical timings in fields or frames, we just haven't managed to consistently use this facility. The relavant function is drm_mode_set_crtcinfo, which fills in the crtc timing information. The first thing to note is that the drm core keeps interlaced modes in frames, but displays modelines in fields. So when the crtc modeset helper copies over the mode into adjusted_mode it will already contain vertical timings in half-frames. The result is that the fixup code in intel_crtc_mode_fixup doesn't actually do anything (in most cases at least). Now gen3+ natively supports interlaced modes and wants the vertical timings in frames. Which is what sdvo already fixes up, at least under some conditions. There are a few other place that demand vertical timings in fields but never actually deal with interlaced modes, so use frame timings for consistency, too. These are: - lvds panel, - dvo encoders - dvo is the only way gen2 could support interlaced mode, but currently we don't support any encoders that do. - tv out - despite that the tv dac sends out an interlaced signal it expects a progressive mode pipe configuration. All these encoders enforce progressive modes by resetting interlace_allowed. Hence we always want crtc vertical timings in frames. Enforce this in our crtc mode_fixup function and rip out any redudant timing computations from the encoders' mode_fixup function. v2-4: Adjust the vertical timings a bit. v5: Split out the 'subtract-one for interlaced' fixes. v6: Clarify issues around tv-out and gen2. Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Tested-by: Christopher Egert <cme3000@gmail.com> Tested-by: Alfonso Fiore <alfonso.fiore@gmail.com> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
381 lines
10 KiB
C
381 lines
10 KiB
C
/*
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* Copyright © 2006-2010 Intel Corporation
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Dave Airlie <airlied@linux.ie>
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* Jesse Barnes <jesse.barnes@intel.com>
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* Chris Wilson <chris@chris-wilson.co.uk>
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*/
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#include "intel_drv.h"
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#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
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void
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intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
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struct drm_display_mode *adjusted_mode)
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{
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adjusted_mode->hdisplay = fixed_mode->hdisplay;
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adjusted_mode->hsync_start = fixed_mode->hsync_start;
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adjusted_mode->hsync_end = fixed_mode->hsync_end;
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adjusted_mode->htotal = fixed_mode->htotal;
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adjusted_mode->vdisplay = fixed_mode->vdisplay;
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adjusted_mode->vsync_start = fixed_mode->vsync_start;
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adjusted_mode->vsync_end = fixed_mode->vsync_end;
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adjusted_mode->vtotal = fixed_mode->vtotal;
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adjusted_mode->clock = fixed_mode->clock;
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drm_mode_set_crtcinfo(adjusted_mode, 0);
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}
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/* adjusted_mode has been preset to be the panel's fixed mode */
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void
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intel_pch_panel_fitting(struct drm_device *dev,
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int fitting_mode,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int x, y, width, height;
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x = y = width = height = 0;
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/* Native modes don't need fitting */
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if (adjusted_mode->hdisplay == mode->hdisplay &&
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adjusted_mode->vdisplay == mode->vdisplay)
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goto done;
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switch (fitting_mode) {
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case DRM_MODE_SCALE_CENTER:
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width = mode->hdisplay;
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height = mode->vdisplay;
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x = (adjusted_mode->hdisplay - width + 1)/2;
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y = (adjusted_mode->vdisplay - height + 1)/2;
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break;
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case DRM_MODE_SCALE_ASPECT:
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/* Scale but preserve the aspect ratio */
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{
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u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
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u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
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if (scaled_width > scaled_height) { /* pillar */
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width = scaled_height / mode->vdisplay;
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if (width & 1)
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width++;
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x = (adjusted_mode->hdisplay - width + 1) / 2;
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y = 0;
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height = adjusted_mode->vdisplay;
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} else if (scaled_width < scaled_height) { /* letter */
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height = scaled_width / mode->hdisplay;
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if (height & 1)
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height++;
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y = (adjusted_mode->vdisplay - height + 1) / 2;
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x = 0;
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width = adjusted_mode->hdisplay;
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} else {
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x = y = 0;
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width = adjusted_mode->hdisplay;
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height = adjusted_mode->vdisplay;
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}
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}
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break;
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default:
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case DRM_MODE_SCALE_FULLSCREEN:
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x = y = 0;
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width = adjusted_mode->hdisplay;
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height = adjusted_mode->vdisplay;
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break;
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}
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done:
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dev_priv->pch_pf_pos = (x << 16) | y;
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dev_priv->pch_pf_size = (width << 16) | height;
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}
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static int is_backlight_combination_mode(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (INTEL_INFO(dev)->gen >= 4)
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return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
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if (IS_GEN2(dev))
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return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
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return 0;
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}
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static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
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{
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u32 val;
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/* Restore the CTL value if it lost, e.g. GPU reset */
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if (HAS_PCH_SPLIT(dev_priv->dev)) {
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val = I915_READ(BLC_PWM_PCH_CTL2);
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if (dev_priv->saveBLC_PWM_CTL2 == 0) {
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dev_priv->saveBLC_PWM_CTL2 = val;
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} else if (val == 0) {
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I915_WRITE(BLC_PWM_PCH_CTL2,
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dev_priv->saveBLC_PWM_CTL2);
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val = dev_priv->saveBLC_PWM_CTL2;
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}
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} else {
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val = I915_READ(BLC_PWM_CTL);
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if (dev_priv->saveBLC_PWM_CTL == 0) {
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dev_priv->saveBLC_PWM_CTL = val;
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dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
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} else if (val == 0) {
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I915_WRITE(BLC_PWM_CTL,
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dev_priv->saveBLC_PWM_CTL);
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I915_WRITE(BLC_PWM_CTL2,
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dev_priv->saveBLC_PWM_CTL2);
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val = dev_priv->saveBLC_PWM_CTL;
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}
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}
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return val;
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}
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u32 intel_panel_get_max_backlight(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 max;
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max = i915_read_blc_pwm_ctl(dev_priv);
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if (max == 0) {
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/* XXX add code here to query mode clock or hardware clock
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* and program max PWM appropriately.
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*/
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printk_once(KERN_WARNING "fixme: max PWM is zero.\n");
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return 1;
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}
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if (HAS_PCH_SPLIT(dev)) {
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max >>= 16;
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} else {
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if (INTEL_INFO(dev)->gen < 4)
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max >>= 17;
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else
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max >>= 16;
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if (is_backlight_combination_mode(dev))
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max *= 0xff;
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}
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DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
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return max;
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}
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u32 intel_panel_get_backlight(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val;
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if (HAS_PCH_SPLIT(dev)) {
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val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
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} else {
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val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
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if (INTEL_INFO(dev)->gen < 4)
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val >>= 1;
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if (is_backlight_combination_mode(dev)) {
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u8 lbpc;
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pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
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val *= lbpc;
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}
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}
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DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
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return val;
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}
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static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
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I915_WRITE(BLC_PWM_CPU_CTL, val | level);
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}
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static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 tmp;
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DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
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if (HAS_PCH_SPLIT(dev))
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return intel_pch_panel_set_backlight(dev, level);
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if (is_backlight_combination_mode(dev)) {
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u32 max = intel_panel_get_max_backlight(dev);
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u8 lbpc;
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lbpc = level * 0xfe / max + 1;
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level /= lbpc;
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pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
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}
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tmp = I915_READ(BLC_PWM_CTL);
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if (INTEL_INFO(dev)->gen < 4)
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level <<= 1;
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tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
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I915_WRITE(BLC_PWM_CTL, tmp | level);
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}
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void intel_panel_set_backlight(struct drm_device *dev, u32 level)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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dev_priv->backlight_level = level;
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if (dev_priv->backlight_enabled)
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intel_panel_actually_set_backlight(dev, level);
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}
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void intel_panel_disable_backlight(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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dev_priv->backlight_enabled = false;
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intel_panel_actually_set_backlight(dev, 0);
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}
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void intel_panel_enable_backlight(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->backlight_level == 0)
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dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
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dev_priv->backlight_enabled = true;
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intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
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}
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static void intel_panel_init_backlight(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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dev_priv->backlight_level = intel_panel_get_backlight(dev);
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dev_priv->backlight_enabled = dev_priv->backlight_level != 0;
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}
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enum drm_connector_status
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intel_panel_detect(struct drm_device *dev)
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{
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#if 0
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struct drm_i915_private *dev_priv = dev->dev_private;
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#endif
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if (i915_panel_ignore_lid)
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return i915_panel_ignore_lid > 0 ?
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connector_status_connected :
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connector_status_disconnected;
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/* opregion lid state on HP 2540p is wrong at boot up,
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* appears to be either the BIOS or Linux ACPI fault */
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#if 0
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/* Assume that the BIOS does not lie through the OpRegion... */
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if (dev_priv->opregion.lid_state)
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return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
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connector_status_connected :
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connector_status_disconnected;
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#endif
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return connector_status_unknown;
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}
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#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
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static int intel_panel_update_status(struct backlight_device *bd)
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{
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struct drm_device *dev = bl_get_data(bd);
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intel_panel_set_backlight(dev, bd->props.brightness);
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return 0;
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}
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static int intel_panel_get_brightness(struct backlight_device *bd)
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{
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struct drm_device *dev = bl_get_data(bd);
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struct drm_i915_private *dev_priv = dev->dev_private;
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return dev_priv->backlight_level;
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}
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static const struct backlight_ops intel_panel_bl_ops = {
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.update_status = intel_panel_update_status,
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.get_brightness = intel_panel_get_brightness,
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};
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int intel_panel_setup_backlight(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct backlight_properties props;
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struct drm_connector *connector;
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intel_panel_init_backlight(dev);
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if (dev_priv->int_lvds_connector)
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connector = dev_priv->int_lvds_connector;
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else if (dev_priv->int_edp_connector)
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connector = dev_priv->int_edp_connector;
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else
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return -ENODEV;
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props.type = BACKLIGHT_RAW;
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props.max_brightness = intel_panel_get_max_backlight(dev);
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dev_priv->backlight =
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backlight_device_register("intel_backlight",
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&connector->kdev, dev,
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&intel_panel_bl_ops, &props);
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if (IS_ERR(dev_priv->backlight)) {
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DRM_ERROR("Failed to register backlight: %ld\n",
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PTR_ERR(dev_priv->backlight));
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dev_priv->backlight = NULL;
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return -ENODEV;
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}
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dev_priv->backlight->props.brightness = intel_panel_get_backlight(dev);
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return 0;
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}
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void intel_panel_destroy_backlight(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->backlight)
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backlight_device_unregister(dev_priv->backlight);
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}
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#else
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int intel_panel_setup_backlight(struct drm_device *dev)
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{
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intel_panel_init_backlight(dev);
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return 0;
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}
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void intel_panel_destroy_backlight(struct drm_device *dev)
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{
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return;
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}
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#endif
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