Dave Jiang d98793b5d4 dmaengine: idxd: fix wq config registers offset programming ... DSA spec v1.1 [1] updated to include a stride size register for WQ configuration that will specify how much space is reserved for the WQ configuration register set. This change is expected to be in the final gen1 DSA hardware. Fix the driver to use WQCFG_OFFSET() for all WQ offset calculation and fixup WQCFG_OFFSET() to use the new calculated wq size. [1]: https://software.intel.com/content/www/us/en/develop/download/intel-data-streaming-accelerator-preliminary-architecture-specification.html Fixes: bfe1d56091 ("dmaengine: idxd: Init and probe for Intel data accelerators") Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/160383444959.48058.14249265538404901781.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2020-10-30 14:10:27 +05:30
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cdev.c	Merge branch 'for-linus' into fixes	2020-08-05 19:02:07 +05:30
device.c	dmaengine: idxd: fix wq config registers offset programming	2020-10-30 14:10:27 +05:30
dma.c	dmaengine: cookie bypass for out of order completion	2020-06-17 19:45:14 +05:30
idxd.h	dmaengine: idxd: fix wq config registers offset programming	2020-10-30 14:10:27 +05:30
init.c	dmaengine: idxd: fix wq config registers offset programming	2020-10-30 14:10:27 +05:30
irq.c	Linux 5.9-rc4	2020-09-11 17:45:36 +05:30
Makefile	dmaengine: idxd: add char driver to expose submission portal to userland	2020-01-24 11:18:45 +05:30
registers.h	dmaengine: idxd: fix wq config registers offset programming	2020-10-30 14:10:27 +05:30
submit.c	dmaengine: idxd: move submission to sbitmap_queue	2020-06-24 12:55:09 +05:30
sysfs.c	dmaengine: idxd: add command status to idxd sysfs attribute	2020-09-03 12:40:12 +05:30