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4cbf47728f
Add device tree bindings for Last-level-cache Tag-and-data (LLC-TAD) unit PMU for Marvell CN10K SoCs. Signed-off-by: Bhaskara Budiredla <bbudiredla@marvell.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211115043506.6679-3-bbudiredla@marvell.com Signed-off-by: Will Deacon <will@kernel.org>
63 lines
1.6 KiB
YAML
63 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell CN10K LLC-TAD performance monitor
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maintainers:
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- Bhaskara Budiredla <bbudiredla@marvell.com>
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description: |
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The Tag-and-Data units (TADs) maintain coherence and contain CN10K
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shared on-chip last level cache (LLC). The tad pmu measures the
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performance of last-level cache. Each tad pmu supports up to eight
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counters.
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The DT setup comprises of number of tad blocks, the sizes of pmu
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regions, tad blocks and overall base address of the HW.
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properties:
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compatible:
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const: marvell,cn10k-tad-pmu
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reg:
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maxItems: 1
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marvell,tad-cnt:
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description: specifies the number of tads on the soc
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$ref: /schemas/types.yaml#/definitions/uint32
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marvell,tad-page-size:
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description: specifies the size of each tad page
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$ref: /schemas/types.yaml#/definitions/uint32
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marvell,tad-pmu-page-size:
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description: specifies the size of page that the pmu uses
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$ref: /schemas/types.yaml#/definitions/uint32
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required:
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- compatible
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- reg
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- marvell,tad-cnt
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- marvell,tad-page-size
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- marvell,tad-pmu-page-size
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additionalProperties: false
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examples:
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- |
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tad {
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#address-cells = <2>;
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#size-cells = <2>;
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tad_pmu@80000000 {
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compatible = "marvell,cn10k-tad-pmu";
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reg = <0x87e2 0x80000000 0x0 0x1000>;
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marvell,tad-cnt = <1>;
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marvell,tad-page-size = <0x1000>;
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marvell,tad-pmu-page-size = <0x1000>;
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};
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};
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