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f29cabf240
The snps,reset-gpio bindings are deprecated in favour of the generic "Ethernet PHY reset" bindings. Replace snps,reset-gpio from the ðmac node with reset-gpios in the ethernet-phy node. The old snps,reset-active-low property is now encoded directly as GPIO flag inside the reset-gpios property. snps,reset-delays-us is converted to reset-assert-us and reset-deassert-us. reset-assert-us is the second cell from snps,reset-delays-us while reset-deassert-us was the third cell. Instead of blindly copying the old values (which seems strange since they gave the PHY one second to come out of reset) over this also updates the delays based on the datasheets: - the Realtek RTL8211F PHY needs a 10ms assert delay (the datasheet mentions: "For a complete PHY reset, this pin must be asserted low for at least 10ms") and a 30ms deassert delay (the datasheet mentions: "Wait for a further 30ms (for internal circuits settling time) before accessing the PHY register". This applies to the following boards: GXBB NanoPi K2, GXBB Odroid-C2, GXBB Vega S95 variants, GXBB Wetek variants, GXL P230, GXM Khadas VIM2, GXM Nexbox A1, GXM Q200, GXM RBox Pro boards. - the ICPlus IP101GR PHY needs a 10ms assert delay (the datasheet mentions: "Trst | Reset period | 10ms") and a deassert delay of 10ms as well (the datasheet mentions: "Tclk_MII_rdy | MII/RMII clock output ready after reset released | 10ms"). This applies to the GXBB Nexbox A95X board. - the Micrel KSZ9031 seems to require a 100us delay but use the same (seemingly safe) values from RTL8211F due to lack of a board to verify this. This applies to the GXBB P200 board. The GXBB P201 board is left out from this conversion because it doesn't have a dedicated PHY node (because it's not clear which PHY is used on that board). Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
371 lines
7.8 KiB
Text
371 lines
7.8 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2017 Andreas Färber
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*/
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/dts-v1/;
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#include "meson-gxbb.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
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aliases {
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serial0 = &uart_AO;
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ethernet0 = ðmac;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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leds {
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compatible = "gpio-leds";
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stat {
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label = "nanopi-k2:blue:stat";
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gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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panic-indicator;
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};
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};
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vdd_5v: regulator-vdd-5v {
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compatible = "regulator-fixed";
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regulator-name = "VDD_5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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vddio_ao18: regulator-vddio-ao18 {
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compatible = "regulator-fixed";
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regulator-name = "VDDIO_AO18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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vddio_ao3v3: regulator-vddio-ao3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VDDIO_AO3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vddio_tf: regulator-vddio-tf {
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compatible = "regulator-gpio";
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regulator-name = "VDDIO_TF";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
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gpios-states = <0>;
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states = <3300000 0>,
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<1800000 1>;
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regulator-settling-time-up-us = <100>;
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regulator-settling-time-down-us = <5000>;
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};
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wifi_32k: wifi-32k {
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compatible = "pwm-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
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};
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sdio_pwrseq: sdio-pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
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clocks = <&wifi_32k>;
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clock-names = "ext_clock";
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};
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vcc1v8: regulator-vcc1v8 {
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compatible = "regulator-fixed";
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regulator-name = "VCC1.8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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vcc3v3: regulator-vcc3v3 {
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compatible = "regulator-fixed";
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regulator-name = "VCC3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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emmc_pwrseq: emmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
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};
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/* CVBS is available on CON1 pin 36, disabled by default */
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cvbs-connector {
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compatible = "composite-video-connector";
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status = "disabled";
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port {
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cvbs_connector_in: endpoint {
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remote-endpoint = <&cvbs_vdac_out>;
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};
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};
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};
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hdmi-connector {
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compatible = "hdmi-connector";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&hdmi_tx_tmds_out>;
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};
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};
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};
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};
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&cec_AO {
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status = "okay";
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pinctrl-0 = <&ao_cec_pins>;
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pinctrl-names = "default";
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hdmi-phandle = <&hdmi_tx>;
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};
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&cvbs_vdac_port {
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cvbs_vdac_out: endpoint {
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remote-endpoint = <&cvbs_connector_in>;
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};
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};
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ðmac {
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status = "okay";
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pinctrl-0 = <ð_rgmii_pins>;
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pinctrl-names = "default";
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phy-handle = <ð_phy0>;
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phy-mode = "rgmii";
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amlogic,tx-delay-ns = <2>;
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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eth_phy0: ethernet-phy@0 {
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/* Realtek RTL8211F (0x001cc916) */
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reg = <0>;
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reset-assert-us = <10000>;
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reset-deassert-us = <30000>;
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reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio_intc>;
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/* MAC_INTR on GPIOZ_15 */
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interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
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};
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};
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};
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&hdmi_tx {
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status = "okay";
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pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>;
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pinctrl-names = "default";
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};
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&hdmi_tx_tmds_port {
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hdmi_tx_tmds_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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&ir {
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status = "okay";
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pinctrl-0 = <&remote_input_ao_pins>;
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pinctrl-names = "default";
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};
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&gpio_ao {
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gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In",
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"VCCK En", "CON1 Header Pin31",
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"I2S Header Pin6", "IR In", "I2S Header Pin7",
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"I2S Header Pin3", "I2S Header Pin4",
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"I2S Header Pin5", "HDMI CEC", "SYS LED",
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/* GPIO_TEST_N */
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"";
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};
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&gpio {
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gpio-line-names = /* Bank GPIOZ */
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"Eth MDIO", "Eth MDC", "Eth RGMII RX Clk",
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"Eth RX DV", "Eth RX D0", "Eth RX D1", "Eth RX D2",
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"Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
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"Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
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"Eth PHY nRESET", "Eth PHY Intc",
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/* Bank GPIOH */
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"HDMI HPD", "HDMI DDC SDA", "HDMI DDC SCL",
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"CON1 Header Pin33",
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/* Bank BOOT */
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"eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
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"eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
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"eMMC Reset", "eMMC CMD",
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"", "", "", "", "eMMC DS",
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"", "",
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/* Bank CARD */
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"SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
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"SDCard D3", "SDCard D2", "SDCard Det",
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/* Bank GPIODV */
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"", "", "", "", "", "", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "", "", "", "",
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"I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
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"VDDEE Regulator", "VCCK Regulator",
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/* Bank GPIOY */
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"CON1 Header Pin7", "CON1 Header Pin11",
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"CON1 Header Pin13", "CON1 Header Pin15",
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"CON1 Header Pin18", "CON1 Header Pin19",
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"CON1 Header Pin22", "CON1 Header Pin21",
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"CON1 Header Pin24", "CON1 Header Pin23",
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"CON1 Header Pin26", "CON1 Header Pin29",
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"CON1 Header Pin32", "CON1 Header Pin8",
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"CON1 Header Pin10", "CON1 Header Pin16",
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"CON1 Header Pin12",
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/* Bank GPIOX */
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"WIFI SDIO D0", "WIFI SDIO D1", "WIFI SDIO D2",
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"WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
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"WIFI Power Enable", "WIFI WAKE HOST",
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"Bluetooth PCM DOUT", "Bluetooth PCM DIN",
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"Bluetooth PCM SYNC", "Bluetooth PCM CLK",
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"Bluetooth UART TX", "Bluetooth UART RX",
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"Bluetooth UART CTS", "Bluetooth UART RTS",
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"", "", "", "WIFI 32K", "Bluetooth Enable",
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"Bluetooth WAKE HOST", "",
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/* Bank GPIOCLK */
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"", "CON1 Header Pin35", "", "";
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};
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&pwm_ef {
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status = "okay";
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pinctrl-0 = <&pwm_e_pins>;
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pinctrl-names = "default";
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clocks = <&clkc CLKID_FCLK_DIV4>;
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clock-names = "clkin0";
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};
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&saradc {
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status = "okay";
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vref-supply = <&vddio_ao18>;
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};
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/* SDIO */
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&sd_emmc_a {
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status = "okay";
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pinctrl-0 = <&sdio_pins>, <&sdio_irq_pins>;
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pinctrl-1 = <&sdio_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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#address-cells = <1>;
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#size-cells = <0>;
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bus-width = <4>;
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cap-sd-highspeed;
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max-frequency = <50000000>;
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non-removable;
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disable-wp;
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mmc-pwrseq = <&sdio_pwrseq>;
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vmmc-supply = <&vddio_ao3v3>;
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vqmmc-supply = <&vddio_ao18>;
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brcmf: wifi@1 {
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compatible = "brcm,bcm4329-fmac";
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reg = <1>;
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};
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};
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/* SD */
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&sd_emmc_b {
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status = "okay";
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pinctrl-0 = <&sdcard_pins>;
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pinctrl-1 = <&sdcard_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-ddr50;
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max-frequency = <100000000>;
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disable-wp;
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cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>;
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vmmc-supply = <&vddio_ao3v3>;
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vqmmc-supply = <&vddio_tf>;
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};
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/* eMMC */
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&sd_emmc_c {
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status = "disabled";
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pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>;
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pinctrl-1 = <&emmc_clk_gate_pins>;
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pinctrl-names = "default", "clk-gate";
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bus-width = <8>;
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max-frequency = <200000000>;
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non-removable;
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disable-wp;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-pwrseq = <&emmc_pwrseq>;
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vmmc-supply = <&vcc3v3>;
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vqmmc-supply = <&vcc1v8>;
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};
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/* DBG_UART */
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&uart_AO {
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status = "okay";
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pinctrl-0 = <&uart_ao_a_pins>;
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pinctrl-names = "default";
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};
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/* Bluetooth on AP6212 */
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&uart_A {
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status = "disabled";
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pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
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pinctrl-names = "default";
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};
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/* 40-pin CON1 */
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&uart_C {
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status = "disabled";
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pinctrl-0 = <&uart_c_pins>;
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pinctrl-names = "default";
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};
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&usb0_phy {
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status = "okay";
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phy-supply = <&vdd_5v>;
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};
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&usb1_phy {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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