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8a7904a672
Some of the SRQ types are created using a WQ, and the WQ requires a
different parameter set to mlx5_umem_find_best_quantized_pgoff() as it has
a 5 bit page_offset.
Add the umem to the mlx5_srq_attr and defer computing the PAS data until
the code has figured out what kind of mailbox to use. Compute the PAS
directly from the umem for each of the four unique mailbox types.
This also avoids allocating memory to store the user PAS, instead it is
written directly to the mailbox as in most other cases.
Fixes: 01949d0109 ("net/mlx5_core: Enable XRCs and SRQs when using ISSI > 0")
Link: https://lore.kernel.org/r/20201115114311.136250-8-leon@kernel.org
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
69 lines
1.5 KiB
C
69 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/*
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* Copyright (c) 2013-2018, Mellanox Technologies. All rights reserved.
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*/
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#ifndef MLX5_IB_SRQ_H
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#define MLX5_IB_SRQ_H
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enum {
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MLX5_SRQ_FLAG_ERR = (1 << 0),
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MLX5_SRQ_FLAG_WQ_SIG = (1 << 1),
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MLX5_SRQ_FLAG_RNDV = (1 << 2),
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};
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struct mlx5_srq_attr {
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u32 type;
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u32 flags;
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u32 log_size;
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u32 wqe_shift;
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u32 log_page_size;
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u32 wqe_cnt;
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u32 srqn;
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u32 xrcd;
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u32 page_offset;
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u32 cqn;
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u32 pd;
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u32 lwm;
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u32 user_index;
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u64 db_record;
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__be64 *pas;
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struct ib_umem *umem;
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u32 tm_log_list_size;
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u32 tm_next_tag;
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u32 tm_hw_phase_cnt;
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u32 tm_sw_phase_cnt;
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u16 uid;
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};
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struct mlx5_ib_dev;
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struct mlx5_core_srq {
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struct mlx5_core_rsc_common common; /* must be first */
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u32 srqn;
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int max;
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size_t max_gs;
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size_t max_avail_gather;
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int wqe_shift;
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void (*event)(struct mlx5_core_srq *srq, enum mlx5_event e);
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u16 uid;
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};
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struct mlx5_srq_table {
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struct notifier_block nb;
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struct xarray array;
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};
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int mlx5_cmd_create_srq(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
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struct mlx5_srq_attr *in);
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int mlx5_cmd_destroy_srq(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq);
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int mlx5_cmd_query_srq(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
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struct mlx5_srq_attr *out);
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int mlx5_cmd_arm_srq(struct mlx5_ib_dev *dev, struct mlx5_core_srq *srq,
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u16 lwm, int is_srq);
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struct mlx5_core_srq *mlx5_cmd_get_srq(struct mlx5_ib_dev *dev, u32 srqn);
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int mlx5_init_srq_table(struct mlx5_ib_dev *dev);
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void mlx5_cleanup_srq_table(struct mlx5_ib_dev *dev);
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#endif /* MLX5_IB_SRQ_H */
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